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| publication number S29NS-P_00 revision a amendment 1 issue date february 20, 2007 S29NS-P mirrorbit tm flash family S29NS-P mirrorbit tm flash family cover sheet s29ns512p s29ns256p s29ns128p 512/256/128 mb (32/16/8 m x 16 bi t), 1.8 v burst simultaneous read/write, multiplexed mirrorbit flash memory data sheet (advance information) notice to readers: this document states the current techni cal specifications regarding the spansion product(s) described herein. each product describ ed herein may be designated as advance information, preliminary, or full production. see notice on data sheet designations for definitions.
2 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) notice on data sheet designations spansion inc. issues data sheets with advance informati on or preliminary designations to advise readers of product information or int ended specifications throu ghout the product life cycle, including development, qualification, initial production, and fu ll production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. the following descriptions of spansion data sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicates that spansion inc. is developing one or more specific products, but has not committed any design to production. information pr esented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spansion inc. therefore places the following c onditions upon advance information content: ?this document contains information on one or mo re products under development at spansion inc. the information is intended to help you evaluate th is product. do not design in this product without contacting the factory. spansion inc. reserves t he right to change or discont inue work on this proposed product without notice.? preliminary the preliminary designation indicates that the produc t development has progressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial produc tion, and the subsequent phases in t he manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these as pects of production under consideration. spansion places the following conditions upon preliminary content: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this doc ument may be revised by subsequent versions or modifications due to changes in technical specifications.? combination some data sheets contain a combination of products with different designations (advance information, preliminary, or full production). this type of docum ent distinguishes these prod ucts and their designations wherever necessary, typically on the first page, t he ordering information page, and pages with the dc characteristics table and the ac erase and program ta ble (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designation is remove d from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as t he addition or deletion of a speed option, temperature range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographical error or incorre ct specification. spansion inc. applies the following conditions to documents in this category: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. spansi on inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or mo difications to the valid comb inations offered may occur.? questions regarding these docum ent designations may be directed to your local sales office. this document contains information on one or more products under development at spansion inc. the information is intended to he lp you evaluate this product. do not design in this product without contacting the factory. spansion inc. reserves the right to change or discontinue work on this proposed pr oduct without notice. publication number S29NS-P_00 revision a amendment 1 issue date february 20, 2007 features ? single 1.8 v read/program/erase (1.70?1.95 v) ? 90 nm mirrorbit technology ? multiplexed data and address for reduced i/o count ? simultaneous read/write operation ? full/half drive output slew rate control ? 32-word write buffer ? sixteen-bank architecture consisting of 64/32/16 mb for ns512/256/128p, respectively ? four 32 kb sectors at the top of memory array (ns256/128p) ? 512 128kb sectors (ns512p), 255/127 128kb sectors (ns256/ 128p) ? programmable linear (8/16/32) with or without wrap around and continuous burst read modes ? secured silicon sector region consisting of 128 words each for factory and customer ? 20-year data retention (typical) ? cycling endurance: 100,000 cycles per sector (typical) ? rdy output indicates data available to system ? command set compatible with jedec (42.4) standard ? hardware (wp#) protection of highest two sectors ? top boot sector configuration (ns256/128p) ? handshaking by monitoring rdy ? offered packages ? ns512p: 64-ball fbga (8 mm x 9.2 mm) ? ns256p/ns128p: 44-ball fbga (6.2 mm x 7.7 mm) ? low v cc write inhibit ? persistent and password methods of advanced sector protection ? write operation status bits indicate program and erase operation completion ? suspend and resume commands for program and erase operations ? unlock bypass program command to reduce programming time ? synchronous or asynchronous program operation, independent of burst control register settings ? v pp input pin to reduce factory programming time ? support for common flash interface (cfi) performance characteristics general description the spansion s29ns512/256/128p are mirrorbit flash products fabricated on 90 nm process technology. these burst mode flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using multiplexed data and address pins . these products can operate up to 108 mhz and use a single v cc of 1.7 v to 1.95 v that makes them ideal for the demanding wireless applications of to day that require higher density, better performance, and lowered power consumption. S29NS-P mirrorbit tm flash family s29ns512p s29ns256p s29ns128p 512/256/128 mb (32/16/8 m x 16 bi t), 1.8 v burst simultaneous read/write, multiplexed mirrorbit flash memory data sheet (advance information) read access times speed option (mhz) 108 max. synch. latency, ns (t iacc )80 max. synch. burst access, ns (t bacc )7.0 max. asynch. access time, ns (t acc )80 max oe# access time, ns (t oe )7.0 current consumption (typical values) continuous burst read @ 108 mhz 42 ma simultaneous operation 108 mhz 60 ma program 30 ma standby mode 20 a typical program & erase times single word programming 30 s effective write buffer programming (v cc ) per word 6 s effective write buffer programming (v pp ) per word 4 s sector erase (16 kword sector) 350 ms sector erase (64 kword sector) 600 ms 4 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2. input/output descrip tions & logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3. block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4. physical dimensions/connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 related documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2 special handling instructions for fbga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5. product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6. device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1 device operation table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.2 asynchronous read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.3 synchronous (burst) read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.4 autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.5 program/erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.6 simultaneous read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.7 writing commands/command sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.8 handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.9 hardware reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.10 software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.11 programmable output slew rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7. advanced sector protection/unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.1 lock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.2 persistent protection bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.3 dynamic protection bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.4 persistent protection bit lock bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.5 password protection method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.6 advanced sector protection software examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.7 hardware data protection methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8. power conservation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8.1 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8.2 automatic sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8.3 hardware reset# inpu t operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8.4 output disable (oe#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9. secured silicon sector flash memory region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.1 factory secured silicon sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.2 customer secured silicon sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1 9.3 secured silicon sector entry and exit command sequences. . . . . . . . . . . . . . . . . . . . . . . . 62 10. electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.2 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.4 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.5 key to switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.6 switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.7 clk characterization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10.8 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10.9 erase and programming performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 11. appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 11.1 common flash memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 12. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 5 data sheet (advance information) figures figure 3.1 simultaneous operation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4.1 64-ball very thin fine-pitch ball grid a rray, s29ns512p top view, balls facing down . . 10 figure 4.2 44-ball very thin fine-pitch ball grid a rray, s29ns256p top view, balls facing down . . 11 figure 4.3 44-ball very thin fine-pitch ball grid a rray, s29ns128p top view, balls facing down . . 11 figure 4.4 vdd064?64-ball very thin fine-pitch ball grid array, s29ns512p. . . . . . . . . . . . . . . . . . 12 figure 4.5 vde044?44-ball very thin fine-pitch ball grid array, s29ns128/256p . . . . . . . . . . . . . . 13 figure 6.1 synchronous read flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 6.2 single word program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 6.3 write buffer programming operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 6.4 sector erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 6.5 write operation status flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 7.1 advanced sector protection/unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 7.2 ppb program/erase algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 7.3 lock register program algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 10.1 maximum negative overshoot waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 10.2 maximum positive overshoot wavefo rm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 10.3 test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 10.4 input waveforms and measurement levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 10.5 v cc power-up diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 10.6 clk characterization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 10.7 8-word linear synchronous single data rate burst with wrap around . . . . . . . . . . . . . . . . 68 figure 10.8 8-word linear single data read synchronous burst without wrap around . . . . . . . . . . . . . 69 figure 10.9 asynchronous mode read with latched addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 10.10 asynchronous mode read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 10.11 reset timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 10.12 asynchronous program operation timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 10.13 chip/sector erase command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 10.14 accelerated unlock bypass programming timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 10.15 data# polling timings (during embedded algorithm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 10.16 toggle bit timings (during embedded algorithm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 10.17 synchronous data polling timings/toggle bit timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 10.18 dq2 vs. dq6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 10.19 latency with boundary crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 10.20 wait state configuration register setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 10.21 back-to-back read/write cycle timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) tables table 2.1 input/output descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 5.1 s29ns512p sector & memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 5.2 s29ns256p sector & memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 5.3 s29ns128p sector & memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 6.1 device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 6.2 address latency for 9 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 6.3 address latency for 8 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 6.4 address latency for 7 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 6.5 address latency for 6 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 6.6 address latency for 5 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 6.7 address latency for 4 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 6.8 address latency for 3 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 6.9 address latency for 2 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 6.10 burst address groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 6.11 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 6.12 autoselect addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 6.13 autoselect entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 6.14 autoselect exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 6.15 single word program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 table 6.16 write buffer program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 6.17 sector erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 6.18 chip erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 6.19 erase suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 table 6.20 erase resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 table 6.21 program suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 table 6.22 program resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 6.23 unlock bypass entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 6.24 unlock bypass program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 6.25 unlock bypass reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 6.26 dq6 and dq2 indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 6.27 write operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 6.28 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 6.29 programmable output slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 7.1 sector protection schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 table 9.1 secured silicon sectorsecure sect or addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 table 9.2 secured silicon sector entry (lld function = lld_secsisectorentrycmd) . . . . . . . . . . . . . .62 table 9.3 secured silicon sector progr am (lld function = lld_programcmd) . . . . . . . . . . . . . . . . . . .62 table 9.4 secured silicon sector exit (lld function = lld_secsisectorexitcmd) . . . . . . . . . . . . . . . . .63 table 10.1 dc characteristics?cmos compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 table 10.2 test specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 table 10.3 v cc power-up with no ramp rate restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 table 10.4 clk characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 table 10.5 synchronous/burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 table 10.6 synchronous wait state requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 table 10.7 asynchronous mode read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 table 10.8 warm reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 table 10.9 erase/program timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 table 10.10 example of programmable wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 table 10.11 erase and programming performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 table 11.1 memory array commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 table 11.2 sector protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 table 11.3 cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 table 11.4 system interface string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 table 11.5 device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 table 11.6 primary vendor-specific extended query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 7 data sheet (advance information) 1. ordering information the ordering part number is formed by a valid combination of the following: notes 1. type 0 is standard. specify other options as required. 2. bga package marking omits leading s29 and packing type designator from ordering part number. valid combinations valid combinations list configurations planned to be supported in volume for this device. consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. s29ns 512 p xx bj w 00 0 packing type 0 = tray (standard; (note 1) ) 3 = 13-inch tape and reel model number 00 = standard temperature range w = wireless (?25c to +85c) package type & material set bj = very thin fine-pitch bga,lead (pb)-free lf35 package speed option (burst frequency) 0p = 66 mhz 0s = 83 mhz ab = 108 mhz process technology p = 90 nm mirrorbit? technology flash density 512 =512 mb 256 =256 mb 128 =128 mb product family s29ns = 1.8 volt-only simultaneous read/write, burst mode multiplexed flash memory valid combinations package type base ordering part number speed option package type, material, & temperature range packing type model number s29ns512p 0p, 0s, ab bjw (lead (pb)-free, lf35) 0, 3 (1) 00 8.0 mm x 9.2 mm, 64-ball s29ns256p 6.2 mm x 7.7 mm, 44-ball s29ns128p 8 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) 2. input/output descriptions & logic symbol table 2.1 identifies the input and output packa ge connections provided on the device. table 2.1 input/output descriptions symbol type description a24 ? a16 input address inputs, s29ns512p a23 ? a16 input address inputs, s29ns256p a22 ? a16 input address inputs, s29ns128p a/dq15 ? a/dq0 i/o multiplexe d address/data input/output ce# input chip enable. asynchronous relative to clk for the burst mode. oe# input output enable. asynchronous relative to clk for the burst mode we# input write enable v cc supply device power supply v ccq supply input/output power supply (must be ramped simultaneously with v cc ) v ss i/o ground v ssq i/o input/output ground nc no connect no connected internally rdy output ready. indicates when valid burst data is ready to be read clk input the first rising edge of clk in conjunction with avd# low latches address input and activates burst mode operation. after the initial word is output, subsequent rising edges of clk increment the internal address counter. clk should remain low during asynchronous access avd# input address valid input. indicates to device that the valid address is present on the address inputs (address bits a15 ? a0 are multiplexed, address bits amax ? a16 are address only). v il = for asynchronous mode, indicates valid address; for burst mode, cause staring address to be latched on rising edge of clk. v ih = device ignores address inputs reset# input hardware reset. low = device resets and returns to reading array data. wp# input write protect. at v il , disables program and erase functions in the four top sectors. should be at v ih for all other conditions. v pp input accelerated input. at v hh , accelerates programming; automatically places device in unlock bypass mode. at v il ,disables all program and erase functions. should be at v ih for all other conditions. rfu reserved reserved for future use february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 9 data sheet (advance information) 3. block diagrams figure 3.1 simultaneous operation circuit notes 1. amax = a24 for ns512p, a23 for ns256p, a22 for ns128p. 2. bank (n) = 15 for ns512p/ ns256p/ ns128p. v ss v cc bank address reset# v pp we# ce# avd# rdy a/dq15?a/dq0 wp# state control & command register bank 1 x-decoder y-decoder latches and control logic bank 0 x-decoder y-decoder latches and control logic dq15?dq0 dq15?dq0 dq15?dq0 dq15?dq0 dq15?dq0 bank (n-1) y-decoder x-decoder latches and control logic bank (n) y-decoder x-decoder latches and control logic oe# status control amax?a0 ?amax?a16 ?amax?a0 ?amax?a16 bank address bank address bank address v ccq v ssq 10 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) 4. physical dimensions/connection diagrams this section shows the i/o designations and package specifications for the opn. 4.1 related documents the following documents contain information relating to the S29NS-P devices. click on the title or go to www.spansion.com , or request a copy from your sales office. ? considerations for x-ray inspection of su rface-mounted flash integrated circuits 4.2 special handling instructions for fbga package special handling is required for flash memory products in fbga packages. flash memory devices in fbga packages may be damaged if exposed to ultrasonic cleaning methods. the package and/or data integrity may be compromised if t he package body is exposed to temperatures above 150c for prolonged periods of time. 64-ball fine-pitch grid array, s29ns512p figure 4.1 64-ball very thin fine-pitch ball grid array, s29ns512p top view, balls facing down figure 2.1. 3 2910 5 47 68 1 13 12 14 11 nc nc b d e f g h j k a c dnu f-vcc a25 f-vss dnu f-vcc a24 f-vss dnu dnu f-rdy f-acc a19 f-vss a21 f-vcc f-clk f-we# a22 a17 f-vccq f-wp# a18 a20 a16 a23 f-adv# f-rst# f-vssq f-ce# f-vss a/dq2 a/dq9 a/dq6 a/dq7 a/dq12 a/dq13 a/dq3 f-oe# a/dq8 a/dq15 a/dq10 f-vccq f-vssq a/dq14 a/dq4 a/dq5 a/dq11 a/dq0 a/dq1 dnu f-vccq dnu dnu dnu f-vssq f-vccq dpd dnu dnu nc nc legend flash only no connect reserved for future use do not use february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 11 data sheet (advance information) 44-ball very thin fine-pitch ball grid array, s29ns256p figure 4.2 44-ball very thin fine-pitch ball grid array, s29ns256p top view, balls facing down 44-ball very thin fine-pitch ball grid array, s29ns128p figure 4.3 44-ball very thin fine-pitch ball grid array, s29ns128p top view, balls facing down a1 rdy a2 a21 a3 v ss a4 clk a5 v cc a6 we# a7 v pp a8 a19 a9 a17 a10 a22 b1 v ccq b2 a16 b3 a20 b4 avd# b5 a23 b6 reset# b7 wp# b8 a18 b9 ce# b10 v ssq d1 a/dq15 d2 a/dq14 d3 v ssq d4 a/dq5 d5 a/dq4 d6 a/dq11 d7 a/dq10 d8 v ccq d9 a/dq1 d10 a/dq0 nc nc nc nc v ss c2 a/dq7 c3 a/dq6 c4 a/dq13 c5 a/dq12 c6 a/dq3 c7 a/dq2 c8 a/dq9 c9 a/dq8 c10 oe# c1 nc nc nc nc a2 a21 a3 v ss a4 clk a5 v cc a6 we# a7 v pp a9 a17 a10 a22 a8 a19 a1 rdy b2 a16 b3 a20 b4 avd# b5 nc b6 reset# b7 wp# b9 ce# b10 v ssq b8 a18 b1 v ccq d2 d3 d4 d5 d6 d7 d9 d10 d8 d1 a/dq14 v ssq a/dq5 a/dq4 a/dq11 a/dq10 a/dq1 a/dq0 v ccq a/dq15 c2 a/dq7 c3 a/dq6 c4 a/dq13 c5 a/dq12 c6 a/dq3 c7 a/dq2 c9 a/dq8 c10 oe# c8 a/dq9 v ss c1 12 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) vdd064?64-ball very thin fine-pitch ball grid array figure 4.4 vdd064?64-ball very thin fine-pitch ball grid array, s29ns512p 3533 \ 16-038.27 \ 12.13.05 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. package vdd 064 jedec n/a 8.00 mm x 9.20 mm nom package symbol min nom max note a 0.86 --- 1.00 overall thickness a1 0.20 --- --- ball height a2 0.66 0.71 0.76 body thickness d 7.90 8.00 8.10 body size e 9.10 9.20 9.30 body size d1 4.50 ball footprint e1 2.50 ball footprint md 10 row matrix size d direction me 6 row matrix size e direction n 64 total ball count ? b 0.25 0.30 0.35 ball diameter e 0.50 ball pitch sd / se 0.25 solder ball placement depopulated solder balls index mark a1 corner side view top view d a 10 c c a e 0.10 b 0.08 c a2 seating plane a1 bottom view e f a b c d 1 2 43 5 6 8 97 nf2 nf4 10 nf3 nf1 a1 corner se 7 e1 d1 0.50 e e sd 7 6 ? b b c m c m ? 0.15 ? 0.05 a 1.00 february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 13 data sheet (advance information) vde44-44-ball very thin fine-pitch ball grid array, 6.2mm x 7.7 mm figure 4.5 vde044?44-ball very thin fine-pitc h ball grid array, s29ns128/256p package vde 044 jedec n/a 7.70 mm x 6.20 mm nom package symbol min nom max note a 0.86 --- 1.00 overall thickness a1 0.20 --- --- ball height a2 0.66 0.71 0.76 body thickness d 7.6 7.7 7.8 body size e 6.1 6.2 6.3 body size d1 4.50 ball footprint e1 1.50 ball footprint md 10 row matrix size d direction me 4 row matrix size e direction n 44 total ball count b 0.25 0.30 0.35 ball diameter e 0.50 bsc. ball pitch sd / se 0.25 bsc. solder ball placement ? depopulated solder balls 3308.2 \ 16-038.9l notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in ? the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. index mark a1 corner side view top view d a 10 a2 a1 e seating plane c 0.10 c b a c 0.08 bottom view nf1 nf3 2 1 3 4 5 6 987 10 a nf2 c d nf4 b d1 sd b e1 se 1.00 e a m m c c 0.05 0.15 b a1 corner 7 7 6 1.00 14 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) 5. product overview the S29NS-P family consists of 512, 256, and 128 mb, 1.8 volts-only, simultaneous read/write burst mode, multiplexed flash device optimized for today?s wirele ss designs that demand a large storage array, rich functionality, and low power consumption. these devices are organized in 32, 16, or 8 mwords of 16 bits each and are capable of continuous, synchronous (burst) read or linear read (8-word, 16- word, or 32-word aligned gr oup) with or without wrap around. these flash devices multiplex the data and ad dresses for reduced i/o count. these products also offer single word programming or a 32-word buffer for programming with program/erase and suspend functionality. additional features include: ? advanced sector protection methods for protecting sectors as required ? 256 words of secured silicon area for storing cust omer and factory secured information. the secured silicon sector is one time programmable. 5.1 memory map the s29ns512/256/128p mb devices consis t of 16 banks organized as shown in ta b l e s 5.1 ? 5.3 . table 5.1 s29ns512p sector & memory address map (sheet 1 of 8) bank sector sector size address range bank sector sector size address range bank 0 sa0 64 kwords 000000h?00ffffh bank 1 sa32 64 kwords 200000h?20ffffh sa1 64 kwords 010000h?01ffffh sa33 64 kwords 210000h?21ffffh sa2 64 kwords 020000h?02ffffh sa34 64 kwords 220000h?22ffffh sa3 64 kwords 030000h?03ffffh sa35 64 kwords 230000h?23ffffh sa4 64 kwords 040000h?04ffffh sa36 64 kwords 240000h?24ffffh sa5 64 kwords 050000h?05ffffh sa37 64 kwords 250000h?25ffffh sa6 64 kwords 060000h?06ffffh sa38 64 kwords 260000h?26ffffh sa7 64 kwords 070000h?07ffffh sa39 64 kwords 270000h?27ffffh sa8 64 kwords 080000h?08ffffh sa40 64 kwords 280000h?28ffffh sa9 64 kwords 090000h?09ffffh sa41 64 kwords 290000h?29ffffh sa10 64 kwords 0a0000h?0affffh sa42 64 kwords 2a0000h?2affffh sa11 64 kwords 0b0000h?0bffffh sa43 64 kwords 2b0000h?2bffffh sa12 64 kwords 0c0000h?0cffffh sa44 64 kwords 2c0000h?2cffffh sa13 64 kwords 0d0000h?0dffffh sa45 64 kwords 2d0000h?2dffffh sa14 64 kwords 0e0000h?0effffh sa46 64 kwords 2e0000h?2effffh sa15 64 kwords 0f0000h?0fffffh sa47 64 kwords 2f0000h?2fffffh sa16 64 kwords 100000h?10ffffh sa48 64 kwords 300000h?30ffffh sa17 64 kwords 110000h?11ffffh sa49 64 kwords 310000h?31ffffh sa18 64 kwords 120000h?12ffffh sa50 64 kwords 320000h?32ffffh sa19 64 kwords 130000h?13ffffh sa51 64 kwords 330000h?33ffffh sa20 64 kwords 140000h?14ffffh sa52 64 kwords 340000h?34ffffh sa21 64 kwords 150000h?15ffffh sa53 64 kwords 350000h?35ffffh sa22 64 kwords 160000h?16ffffh sa54 64 kwords 360000h?36ffffh sa23 64 kwords 170000h?17ffffh sa55 64 kwords 370000h?37ffffh sa24 64 kwords 180000h?18ffffh sa56 64 kwords 380000h?38ffffh sa25 64 kwords 190000h?19ffffh sa57 64 kwords 390000h?39ffffh sa26 64 kwords 1a0000h?1affffh sa58 64 kwords 3a0000h?3affffh sa27 64 kwords 1b0000h?1bffffh sa59 64 kwords 3b0000h?3bffffh sa28 64 kwords 1c0000h?1cffffh sa60 64 kwords 3c0000h?3cffffh sa29 64 kwords 1d0000h?1dffffh sa61 64 kwords 3d0000h?3dffffh sa30 64 kwords 1e0000h?1effffh sa62 64 kwords 3e0000h?3effffh sa31 64 kwords 1f0000h?1fffffh sa63 64 kwords 3f0000h?3fffffh february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 15 data sheet (advance information) bank 2 sa64 64 kwords 400000h?40ffffh bank 3 sa96 64 k words 600000h?60ffffh sa65 64 kwords 410000h?41ffffh sa97 64 k words 610000h?61ffffh sa66 64 kwords 420000h?42ffffh sa98 64 k words 620000h?62ffffh sa67 64 kwords 430000h?43ffffh sa99 64 k words 630000h?63ffffh sa68 64 kwords 440000h?44ffffh sa100 64 k words 640000h?64ffffh sa69 64 kwords 450000h?45ffffh sa101 64 k words 650000h?65ffffh sa70 64 kwords 460000h?46ffffh sa102 64 k words 660000h?66ffffh sa71 64 kwords 470000h?47ffffh sa103 64 k words 670000h?67ffffh sa72 64 kwords 480000h?48ffffh sa104 64 k words 680000h?68ffffh sa73 64 kwords 490000h?49ffffh sa105 64 k words 690000h?69ffffh sa74 64 kwords 4a0000h?4affffh sa106 64 k words 6a0000h?6affffh sa75 64 kwords 4b0000h?4bffffh sa107 64 k words 6b0000h?6bffffh sa76 64 kwords 4c0000h?4cffffh sa108 64 k words 6c0000h?6cffffh sa77 64 kwords 4d0000h?4dffffh sa109 64 k words 6d0000h?6dffffh sa78 64 kwords 4e0000h?4effffh sa110 64 k words 6e0000h?6effffh sa79 64 kwords 4f0000h?4fffffh sa111 64 k words 6f0000h?6fffffh sa80 64 kwords 500000h?50ffffh sa112 64 k words 700000h?70ffffh sa81 64 kwords 510000h?51ffffh sa113 64 k words 710000h?71ffffh sa82 64 kwords 520000h?52ffffh sa114 64 k words 720000h?72ffffh sa83 64 kwords 530000h?53ffffh sa115 64 k words 730000h?73ffffh sa84 64 kwords 540000h?54ffffh sa116 64 k words 740000h?74ffffh sa85 64 kwords 550000h?55ffffh sa117 64 k words 750000h?75ffffh sa86 64 kwords 560000h?56ffffh sa118 64 k words 760000h?76ffffh sa87 64 kwords 570000h?57ffffh sa119 64 k words 770000h?77ffffh sa88 64 kwords 580000h?58ffffh sa120 64 k words 780000h?78ffffh sa89 64 kwords 590000h?59ffffh sa121 64 k words 790000h?79ffffh sa90 64 kwords 5a0000h?5affffh sa122 64 k words 7a0000h?7affffh sa91 64 kwords 5b0000h?5bffffh sa123 64 k words 7b0000h?7bffffh sa92 64 kwords 5c0000h?5cffffh sa124 64 k words 7c0000h?7cffffh sa93 64 kwords 5d0000h?5dffffh sa125 64 k words 7d0000h?7dffffh sa94 64 kwords 5e0000h?5effffh sa126 64 k words 7e0000h?7effffh sa95 64 kwords 5f0000h?5fffffh sa127 64 k words 7f0000h?7fffffh table 5.1 s29ns512p sector & memory address map (sheet 2 of 8) bank sector sector size address range bank sector sector size address range 16 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) bank 4 sa128 64 kwords 800000h?80ffffh bank 5 sa160 64 kwords a00000h?a0ffffh sa129 64 kwords 810000h?81ffffh sa161 64 kwords a10000h?a1ffffh sa130 64 kwords 820000h?82ffffh sa162 64 kwords a20000h?a2ffffh sa131 64 kwords 830000h?83ffffh sa163 64 kwords a30000h?a3ffffh sa132 64 kwords 840000h?84ffffh sa164 64 kwords a40000h?a4ffffh sa133 64 kwords 850000h?85ffffh sa165 64 kwords a50000h?a5ffffh sa134 64 kwords 860000h?86ffffh sa166 64 kwords a60000h?a6ffffh sa135 64 kwords 870000h?87ffffh sa167 64 kwords a70000h?a7ffffh sa136 64 kwords 880000h?88ffffh sa168 64 kwords a80000h?a8ffffh sa137 64 kwords 890000h?89ffffh sa169 64 kwords a90000h?a9ffffh sa138 64 kwords 8a0000h?8affffh sa170 64 kwords aa0000h?aaffffh sa139 64 kwords 8b0000h?8bffffh sa171 64 kwords ab0000h?abffffh sa140 64 kwords 8c0000h?8cffffh sa172 64 kwords ac0000h?acffffh sa141 64 kwords 8d0000h?8dffffh sa173 64 kwords ad0000h?adffffh sa142 64 kwords 8e0000h?8effffh sa174 64 kwords ae0000h?aeffffh sa143 64 kwords 8f0000h?8fffffh sa175 64 kwords af0000h?afffffh sa144 64 kwords 900000h?90ffffh sa176 64 kwords b00000h?b0ffffh sa145 64 kwords 910000h?91ffffh sa177 64 kwords b10000h?b1ffffh sa146 64 kwords 920000h?92ffffh sa178 64 kwords b20000h?b2ffffh sa147 64 kwords 930000h?93ffffh sa179 64 kwords b30000h?b3ffffh sa148 64 kwords 940000h?94ffffh sa180 64 kwords b40000h?b4ffffh sa149 64 kwords 950000h?95ffffh sa181 64 kwords b50000h?b5ffffh sa150 64 kwords 960000h?96ffffh sa182 64 kwords b60000h?b6ffffh sa151 64 kwords 970000h?97ffffh sa183 64 kwords b70000h?b7ffffh sa152 64 kwords 980000h?98ffffh sa184 64 kwords b80000h?b8ffffh sa153 64 kwords 990000h?99ffffh sa185 64 kwords b90000h?b9ffffh sa154 64 kwords 9a0000h?9affffh sa186 64 kwords ba0000h?baffffh sa155 64 kwords 9b0000h?9bffffh sa187 64 kwords bb0000h?bbffffh sa156 64 kwords 9c0000h?9cffffh sa188 64 kwords bc0000h?bcffffh sa157 64 kwords 9d0000h?9dffffh sa189 64 kwords bd0000h?bdffffh sa158 64 kwords 9e0000h?9effffh sa190 64 kwords be0000h?beffffh sa159 64 kwords 9f0000h?9fffffh sa191 64 kwords bf0000h?bfffffh table 5.1 s29ns512p sector & memory address map (sheet 3 of 8) bank sector sector size address range bank sector sector size address range february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 17 data sheet (advance information) bank 6 sa192 64 kwords c00000h?c0ffffh bank 7 sa224 64 k words e00000h?e0ffffh sa193 64 kwords c10000h?c1ffffh sa225 64 k words e10000h?e1ffffh sa194 64 kwords c20000h?c2ffffh sa226 64 k words e20000h?e2ffffh sa195 64 kwords c30000h?c3ffffh sa227 64 k words e30000h?e3ffffh sa196 64 kwords c40000h?c4ffffh sa228 64 k words e40000h?e4ffffh sa197 64 kwords c50000h?c5ffffh sa229 64 k words e50000h?e5ffffh sa198 64 kwords c60000h?c6ffffh sa230 64 k words e60000h?e6ffffh sa199 64 kwords c70000h?c7ffffh sa231 64 k words e70000h?e7ffffh sa200 64 kwords c80000h?c8ffffh sa232 64 k words e80000h?e8ffffh sa201 64 kwords c90000h?c9ffffh sa233 64 k words e90000h?e9ffffh sa202 64 kwords ca0000h?caffffh sa234 64 k words ea0000h?eaffffh sa203 64 kwords cb0000h?cbffffh sa235 64 k words eb0000h?ebffffh sa204 64 kwords cc0000h?ccffffh sa236 64 k words ec0000h?ecffffh sa205 64 kwords cd0000h?cdffffh sa237 64 k words ed0000h?edffffh sa206 64 kwords ce0000h?ceffffh sa238 64 k words ee0000h?eeffffh sa207 64 kwords cf0000h?cfffffh sa239 64 k words ef0000h?efffffh sa208 64 kwords d00000h?d0ffffh sa240 64 k words f00000h?f0ffffh sa209 64 kwords d10000h?d1ffffh sa241 64 k words f10000h?f1ffffh sa210 64 kwords d20000h?d2ffffh sa242 64 k words f20000h?f2ffffh sa211 64 kwords d30000h?d3ffffh sa243 64 k words f30000h?f3ffffh sa212 64 kwords d40000h?d4ffffh sa244 64 k words f40000h?f4ffffh sa213 64 kwords d50000h?d5ffffh sa245 64 k words f50000h?f5ffffh sa214 64 kwords d60000h?d6ffffh sa246 64 k words f60000h?f6ffffh sa215 64 kwords d70000h?d7ffffh sa247 64 k words f70000h?f7ffffh sa216 64 kwords d80000h?d8ffffh sa248 64 k words f80000h?f8ffffh sa217 64 kwords d90000h?d9ffffh sa249 64 k words f90000h?f9ffffh sa218 64 kwords da0000h?daffffh sa250 64 k words fa0000h?faffffh sa219 64 kwords db0000h?dbffffh sa251 64 k words fb0000h?fbffffh sa220 64 kwords dc0000h?dcffffh sa252 64 k words fc0000h?fcffffh sa221 64 kwords dd0000h?ddffffh sa253 64 k words fd0000h?fdffffh sa222 64 kwords de0000h?deffffh sa254 64 k words fe0000h?feffffh sa223 64 kwords df0000h?dfffffh sa255 64 k words ff0000h?ffffffh table 5.1 s29ns512p sector & memory address map (sheet 4 of 8) bank sector sector size address range bank sector sector size address range 18 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) bank 8 sa256 64 kwords 1000000h-100ffffh bank 9 sa288 64 kwords 1200000h-120ffffh sa257 64 kwords 1010000h-101ffffh sa289 64 kwords 1210000h-121ffffh sa258 64 kwords 1020000h-102ffffh sa290 64 kwords 1220000h-122ffffh sa259 64 kwords 1030000h-103ffffh sa291 64 kwords 1230000h-123ffffh sa260 64 kwords 1040000h-104ffffh sa292 64 kwords 1240000h-124ffffh sa261 64 kwords 1050000h-105ffffh sa293 64 kwords 1250000h-125ffffh sa262 64 kwords 1060000h-106ffffh sa294 64 kwords 1260000h-126ffffh sa263 64 kwords 1070000h-107ffffh sa295 64 kwords 1270000h-127ffffh sa264 64 kwords 1030000h-108ffffh sa296 64 kwords 1230000h-128ffffh sa265 64 kwords 1090000h-109ffffh sa297 64 kwords 1290000h-129ffffh sa266 64 kwords 10a0000h-10affffh sa298 64 kwords 12a0000h-12affffh sa267 64 kwords 10b0000h-10bffffh sa299 64 kwords 12b0000h-12bffffh sa268 64 kwords 10c0000h-10cffffh sa300 64 kwords 12c0000h-12cffffh sa269 64 kwords 10d0000h-10dffffh sa301 64 kwords 12d0000h-12dffffh sa270 64 kwords 10e0000h-10effffh sa302 64 kwords 12e0000h-12effffh sa271 64 kwords 10f0000h-10fffffh sa303 64 kwords 12f0000h-12fffffh sa272 64 kwords 1100000h-110ffffh sa304 64 kwords 1300000h-130ffffh sa273 64 kwords 1110000h-111ffffh sa305 64 kwords 1310000h-131ffffh sa274 64 kwords 1120000h-112ffffh sa306 64 kwords 1320000h-132ffffh sa275 64 kwords 1130000h-113ffffh sa307 64 kwords 1330000h-133ffffh sa276 64 kwords 1140000h-114ffffh sa308 64 kwords 1340000h-134ffffh sa277 64 kwords 1150000h-115ffffh sa309 64 kwords 1350000h-135ffffh sa278 64 kwords 1160000h-116ffffh sa310 64 kwords 1360000h-136ffffh sa279 64 kwords 1170000h-117ffffh sa311 64 kwords 1370000h-137ffffh sa280 64 kwords 1180000h-118ffffh sa312 64 kwords 1380000h-138ffffh sa281 64 kwords 1190000h-119ffffh sa313 64 kwords 1390000h-139ffffh sa282 64 kwords 11a0000h-11affffh sa314 64 kwords 13a0000h-13affffh sa283 64 kwords 11b0000h-11bffffh sa315 64 kwords 13b0000h-13bffffh sa284 64 kwords 11c0000h-11cffffh sa316 64 kwords 13c0000h-13cffffh sa285 64 kwords 11d0000h-11dffffh sa317 64 kwords 13d0000h-13dffffh sa286 64 kwords 11e0000h-11effffh sa318 64 kwords 13e0000h-13effffh sa287 64 kwords 11f0000h-11fffffh sa319 64 kwords 13f0000h-13fffffh table 5.1 s29ns512p sector & memory address map (sheet 5 of 8) bank sector sector size address range bank sector sector size address range february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 19 data sheet (advance information) bank 10 sa320 64 kwords 1400000h-140ffffh bank 11 sa352 64 k words 1600000h-160ffffh sa321 64 kwords 1410000h-141ffffh sa353 64 k words 1610000h-161ffffh sa322 64 kwords 1420000h-142ffffh sa354 64 k words 1620000h-162ffffh sa323 64 kwords 1430000h-143ffffh sa355 64 k words 1630000h-163ffffh sa324 64 kwords 1440000h-144ffffh sa356 64 k words 1640000h-164ffffh sa325 64 kwords 1450000h-145ffffh sa357 64 k words 1650000h-165ffffh sa326 64 kwords 1460000h-146ffffh sa358 64 k words 1660000h-166ffffh sa327 64 kwords 1470000h-147ffffh sa359 64 k words 1670000h-167ffffh sa328 64 kwords 1430000h-148ffffh sa360 64 k words 1630000h-168ffffh sa329 64 kwords 1490000h-149ffffh sa361 64 k words 1690000h-169ffffh sa330 64 kwords 14a0000h-14affffh sa362 64 k words 16a0000h-16affffh sa331 64 kwords 14b0000h-14bffffh sa363 64 k words 16b0000h-16bffffh sa332 64 kwords 14c0000h-14cffffh sa364 64 k words 16c0000h-16cffffh sa333 64 kwords 14d0000h-14dffffh sa365 64 k words 16d0000h-16dffffh sa334 64 kwords 14e0000h-14effffh sa366 64 k words 16e0000h-16effffh sa335 64 kwords 14f0000h-14fffffh sa367 64 k words 16f0000h-16fffffh sa336 64 kwords 1500000h-150ffffh sa368 64 k words 1700000h-170ffffh sa337 64 kwords 1510000h-151ffffh sa369 64 k words 1710000h-171ffffh sa338 64 kwords 1520000h-152ffffh sa370 64 k words 1720000h-172ffffh sa339 64 kwords 1530000h-153ffffh sa371 64 k words 1730000h-173ffffh sa340 64 kwords 1540000h-154ffffh sa372 64 k words 1740000h-174ffffh sa341 64 kwords 1550000h-155ffffh sa373 64 k words 1750000h-175ffffh sa342 64 kwords 1560000h-156ffffh sa374 64 k words 1760000h-176ffffh sa343 64 kwords 1570000h-157ffffh sa375 64 k words 1770000h-177ffffh sa344 64 kwords 1580000h-158ffffh sa376 64 k words 1780000h-178ffffh sa345 64 kwords 1590000h-159ffffh sa377 64 k words 1790000h-179ffffh sa346 64 kwords 15a0000h-15affffh sa378 64 k words 17a0000h-17affffh sa347 64 kwords 15b0000h-15bffffh sa379 64 k words 17b0000h-17bffffh sa348 64 kwords 15c0000h-15cffffh sa380 64 k words 15c0000h-17cffffh sa349 64 kwords 15d0000h-15dffffh sa381 64 k words 17d0000h-17dffffh sa350 64 kwords 15e0000h-15effffh sa382 64 k words 17e0000h-17effffh sa351 64 kwords 15f0000h-15fffffh sa383 64 k words 17f0000h-17fffffh table 5.1 s29ns512p sector & memory address map (sheet 6 of 8) bank sector sector size address range bank sector sector size address range 20 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) bank 12 sa384 64 kwords 1800000h-180ffffh bank 13 sa416 64 kwords 1a00000h-1a0ffffh sa385 64 kwords 1810000h-181ffffh sa417 64 kwords 1a10000h-1a1ffffh sa386 64 kwords 1820000h-182ffffh sa418 64 kwords 1a20000h-1a2ffffh sa387 64 kwords 1830000h-183ffffh sa419 64 kwords 1a30000h-1a3ffffh sa388 64 kwords 1840000h-184ffffh sa420 64 kwords 1a40000h-1a4ffffh sa389 64 kwords 1850000h-185ffffh sa421 64 kwords 1a50000h-1a5ffffh sa390 64 kwords 1860000h-186ffffh sa422 64 kwords 1a60000h-1a6ffffh sa391 64 kwords 1870000h-187ffffh sa423 64 kwords 1a70000h-1a7ffffh sa392 64 kwords 1830000h-188ffffh sa424 64 kwords 1a30000h-1a8ffffh sa393 64 kwords 1890000h-189ffffh sa425 64 kwords 1a90000h-1a9ffffh sa394 64 kwords 18a0000h-18affffh sa426 64 kwords 1aa0000h-1aaffffh sa395 64 kwords 18b0000h-18bffffh sa427 64 kwords 1ab0000h-1abffffh sa396 64 kwords 18c0000h-18cffffh sa428 64 kwords 1ac0000h-1acffffh sa397 64 kwords 18d0000h-18dffffh sa429 64 kwords 1ad0000h-1adffffh sa398 64 kwords 18e0000h-18effffh sa430 64 kwords 1ae0000h-1aeffffh sa399 64 kwords 18f0000h-18fffffh sa431 64 kwords 1af0000h-1afffffh sa400 64 kwords 1900000h-190ffffh sa432 64 kwords 1b00000h-1b0ffffh sa401 64 kwords 1910000h-191ffffh sa433 64 kwords 1b10000h-1b1ffffh sa402 64 kwords 1920000h-192ffffh sa434 64 kwords 1b20000h-1b2ffffh sa403 64 kwords 1930000h-193ffffh sa435 64 kwords 1b30000h-1b3ffffh sa404 64 kwords 1940000h-194ffffh sa436 64 kwords 1b40000h-1b4ffffh sa405 64 kwords 1950000h-195ffffh sa437 64 kwords 1b50000h-1b5ffffh sa406 64 kwords 1960000h-196ffffh sa438 64 kwords 1b60000h-1b6ffffh sa407 64 kwords 1970000h-197ffffh sa439 64 kwords 1b70000h-1b7ffffh sa408 64 kwords 1980000h-198ffffh sa440 64 kwords 1b80000h-1b8ffffh sa409 64 kwords 1990000h-199ffffh sa441 64 kwords 1b90000h-1b9ffffh sa410 64 kwords 19a0000h-19affffh sa442 64 kwords 1ba0000h-1baffffh sa411 64 kwords 19b0000h-19bffffh sa443 64 kwords 1bb0000h-1bbffffh sa412 64 kwords 19c0000h-19cffffh sa444 64 kwords 1bc0000h-1bcffffh sa413 64 kwords 19d0000h-19dffffh sa445 64 kwords 1bd0000h-1bdffffh sa414 64 kwords 19e0000h-19effffh sa446 64 kwords 1be0000h-1beffffh sa415 64 kwords 19f0000h-19fffffh sa447 64 kwords 1bf0000h-1bfffffh table 5.1 s29ns512p sector & memory address map (sheet 7 of 8) bank sector sector size address range bank sector sector size address range february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 21 data sheet (advance information) bank 14 sa448 64 kwords 1c00000h-1c0ffffh bank 15 sa480 64 k words 1e00000h-1e0ffffh sa449 64 kwords 1c10000h-1c1ffffh sa481 64 k words 1e10000h-1e1ffffh sa450 64 kwords 1c20000h-1c2ffffh sa482 64 k words 1e20000h-1e2ffffh sa451 64 kwords 1c30000h-1c3ffffh sa483 64 k words 1e30000h-1e3ffffh sa452 64 kwords 1c40000h-1c4ffffh sa484 64 k words 1e40000h-1e4ffffh sa453 64 kwords 1c50000h-1c5ffffh sa485 64 k words 1e50000h-1e5ffffh sa454 64 kwords 1c60000h-1c6ffffh sa486 64 k words 1e60000h-1e6ffffh sa455 64 kwords 1c70000h-1c7ffffh sa487 64 k words 1e70000h-1e7ffffh sa456 64 kwords 1c30000h-1c8ffffh sa488 64 k words 1e30000h-1e8ffffh sa457 64 kwords 1c90000h-1c9ffffh sa489 64 k words 1e90000h-1e9ffffh sa458 64 kwords 1ca0000h-1caffffh sa490 64 k words 1ea0000h-1eaffffh sa459 64 kwords 1cb0000h-1cbffffh sa491 64 k words 1eb0000h-1ebffffh sa460 64 kwords 1cc0000h-1ccffffh sa492 64 k words 1ec0000h-1ecffffh sa461 64 kwords 1cd0000h-1cdffffh sa493 64 k words 1ed0000h-1edffffh sa462 64 kwords 1ce0000h-1ceffffh sa494 64 k words 1ee0000h-1eeffffh sa463 64 kwords 1cf0000h-1cfffffh sa495 64 k words 1ef0000h-1efffffh sa464 64 kwords 1d00000h-1d0ffffh sa496 64 k words 1f00000h-1f0ffffh sa465 64 kwords 1d10000h-1d1ffffh sa497 64 k words 1f10000h-1f1ffffh sa466 64 kwords 1d20000h-1d2ffffh sa498 64 k words 1f20000h-1f2ffffh sa467 64 kwords 1d30000h-1d3ffffh sa499 64 k words 1f30000h-1f3ffffh sa468 64 kwords 1d40000h-1d4ffffh sa500 64 k words 1f40000h-1f4ffffh sa469 64 kwords 1d50000h-1d5ffffh sa501 64 k words 1f50000h-1f5ffffh sa470 64 kwords 1d60000h-1d6ffffh sa502 64 k words 1f60000h-1f6ffffh sa471 64 kwords 1d70000h-1d7ffffh sa503 64 k words 1f70000h-1f7ffffh sa472 64 kwords 1d80000h-1d8ffffh sa504 64 k words 1f80000h-1f8ffffh sa473 64 kwords 1d90000h-1d9ffffh sa505 64 k words 1f90000h-1f9ffffh sa474 64 kwords 1da0000h-1daffffh sa506 64 k words 1fa0000h-1faffffh sa475 64 kwords 1db0000h-1dbffffh sa507 64 k words 1fb0000h-1fbffffh sa476 64 kwords 1dc0000h-1dcffffh sa508 64 k words 1fc0000h-1fcffffh sa477 64 kwords 1dd0000h-1ddffffh sa509 64 k words 1fd0000h-1fdffffh sa478 64 kwords 1de0000h-1deffffh sa510 64 k words 1fe0000h-1feffffh sa479 64 kwords 1df0000h-1dfffffh sa511 64 k words 1ff0000h-1ffffffh table 5.1 s29ns512p sector & memory address map (sheet 8 of 8) bank sector sector size address range bank sector sector size address range 22 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) table 5.2 s29ns256p sector & memory address map (sheet 1 of 3) bank sector sector size address range bank sector sector size address range bank 0 sa0 64 kwords 000000h?00ffffh bank 2 sa32 64 kwords 200000h?20ffffh sa1 64 kwords 010000h?01ffffh sa33 64 kwords 210000h?21ffffh sa2 64 kwords 020000h?02ffffh sa34 64 kwords 220000h?22ffffh sa3 64 kwords 030000h?03ffffh sa35 64 kwords 230000h?23ffffh sa4 64 kwords 040000h?04ffffh sa36 64 kwords 240000h?24ffffh sa5 64 kwords 050000h?05ffffh sa37 64 kwords 250000h?25ffffh sa6 64 kwords 060000h?06ffffh sa38 64 kwords 260000h?26ffffh sa7 64 kwords 070000h?07ffffh sa39 64 kwords 270000h?27ffffh sa8 64 kwords 080000h?08ffffh sa40 64 kwords 280000h?28ffffh sa9 64 kwords 090000h?09ffffh sa41 64 kwords 290000h?29ffffh sa10 64 kwords 0a0000h?0affffh sa42 64 kwords 2a0000h?2affffh sa11 64 kwords 0b0000h?0bffffh sa43 64 kwords 2b0000h?2bffffh sa12 64 kwords 0c0000h?0cffffh sa44 64 kwords 2c0000h?2cffffh sa13 64 kwords 0d0000h?0dffffh sa45 64 kwords 2d0000h?2dffffh sa14 64 kwords 0e0000h?0effffh sa46 64 kwords 2e0000h?2effffh sa15 64 kwords 0f0000h?0fffffh sa47 64 kwords 2f0000h?2fffffh bank 1 sa16 64 kwords 100000h?10ffffh bank 3 sa48 64 kwords 300000h?30ffffh sa17 64 kwords 110000h?11ffffh sa49 64 kwords 310000h?31ffffh sa18 64 kwords 120000h?12ffffh sa50 64 kwords 320000h?32ffffh sa19 64 kwords 130000h?13ffffh sa51 64 kwords 330000h?33ffffh sa20 64 kwords 140000h?14ffffh sa52 64 kwords 340000h?34ffffh sa21 64 kwords 150000h?15ffffh sa53 64 kwords 350000h?35ffffh sa22 64 kwords 160000h?16ffffh sa54 64 kwords 360000h?36ffffh sa23 64 kwords 170000h?17ffffh sa55 64 kwords 370000h?37ffffh sa24 64 kwords 180000h?18ffffh sa56 64 kwords 380000h?38ffffh sa25 64 kwords 190000h?19ffffh sa57 64 kwords 390000h?39ffffh sa26 64 kwords 1a0000h?1affffh sa58 64 kwords 3a0000h?3affffh sa27 64 kwords 1b0000h?1bffffh sa59 64 kwords 3b0000h?3bffffh sa28 64 kwords 1c0000h?1cffffh sa60 64 kwords 3c0000h?3cffffh sa29 64 kwords 1d0000h?1dffffh sa61 64 kwords 3d0000h?3dffffh sa30 64 kwords 1e0000h?1effffh sa62 64 kwords 3e0000h?3effffh sa31 64 kwords 1f0000h?1fffffh sa63 64 kwords 3f0000h?3fffffh bank 4 sa64 64 kwords 400000h?40ffffh bank 6 sa96 64 k words 600000h?60ffffh sa65 64 kwords 410000h?41ffffh sa97 64 k words 610000h?61ffffh sa66 64 kwords 420000h?42ffffh sa98 64 k words 620000h?62ffffh sa67 64 kwords 430000h?43ffffh sa99 64 k words 630000h?63ffffh sa68 64 kwords 440000h?44ffffh sa100 64 k words 640000h?64ffffh sa69 64 kwords 450000h?45ffffh sa101 64 k words 650000h?65ffffh sa70 64 kwords 460000h?46ffffh sa102 64 k words 660000h?66ffffh sa71 64 kwords 470000h?47ffffh sa103 64 k words 670000h?67ffffh sa72 64 kwords 480000h?48ffffh sa104 64 k words 680000h?68ffffh sa73 64 kwords 490000h?49ffffh sa105 64 k words 690000h?69ffffh sa74 64 kwords 4a0000h?4affffh sa106 64 k words 6a0000h?6affffh sa75 64 kwords 4b0000h?4bffffh sa107 64 k words 6b0000h?6bffffh sa76 64 kwords 4c0000h?4cffffh sa108 64 k words 6c0000h?6cffffh sa77 64 kwords 4d0000h?4dffffh sa109 64 k words 6d0000h?6dffffh sa78 64 kwords 4e0000h?4effffh sa110 64 k words 6e0000h?6effffh sa79 64 kwords 4f0000h?4fffffh sa111 64 k words 6f0000h?6fffffh february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 23 data sheet (advance information) bank 5 sa80 64 kwords 500000h?50ffffh bank 7 sa112 64 k words 700000h?70ffffh sa81 64 kwords 510000h?51ffffh sa113 64 k words 710000h?71ffffh sa82 64 kwords 520000h?52ffffh sa114 64 k words 720000h?72ffffh sa83 64 kwords 530000h?53ffffh sa115 64 k words 730000h?73ffffh sa84 64 kwords 540000h?54ffffh sa116 64 k words 740000h?74ffffh sa85 64 kwords 550000h?55ffffh sa117 64 k words 750000h?75ffffh sa86 64 kwords 560000h?56ffffh sa118 64 k words 760000h?76ffffh sa87 64 kwords 570000h?57ffffh sa119 64 k words 770000h?77ffffh sa88 64 kwords 580000h?58ffffh sa120 64 k words 780000h?78ffffh sa89 64 kwords 590000h?59ffffh sa121 64 k words 790000h?79ffffh sa90 64 kwords 5a0000h?5affffh sa122 64 k words 7a0000h?7affffh sa91 64 kwords 5b0000h?5bffffh sa123 64 k words 7b0000h?7bffffh sa92 64 kwords 5c0000h?5cffffh sa124 64 k words 7c0000h?7cffffh sa93 64 kwords 5d0000h?5dffffh sa125 64 k words 7d0000h?7dffffh sa94 64 kwords 5e0000h?5effffh sa126 64 k words 7e0000h?7effffh sa95 64 kwords 5f0000h?5fffffh sa127 64 k words 7f0000h?7fffffh bank 8 sa128 64 kwords 800000h?80ffffh bank 10 sa160 64 kwords a00000h?a0ffffh sa129 64 kwords 810000h?81ffffh sa161 64 kwords a10000h?a1ffffh sa130 64 kwords 820000h?82ffffh sa162 64 kwords a20000h?a2ffffh sa131 64 kwords 830000h?83ffffh sa163 64 kwords a30000h?a3ffffh sa132 64 kwords 840000h?84ffffh sa164 64 kwords a40000h?a4ffffh sa133 64 kwords 850000h?85ffffh sa165 64 kwords a50000h?a5ffffh sa134 64 kwords 860000h?86ffffh sa166 64 kwords a60000h?a6ffffh sa135 64 kwords 870000h?87ffffh sa167 64 kwords a70000h?a7ffffh sa136 64 kwords 880000h?88ffffh sa168 64 kwords a80000h?a8ffffh sa137 64 kwords 890000h?89ffffh sa169 64 kwords a90000h?a9ffffh sa138 64 kwords 8a0000h?8affffh sa170 64 kwords aa0000h?aaffffh sa139 64 kwords 8b0000h?8bffffh sa171 64 kwords ab0000h?abffffh sa140 64 kwords 8c0000h?8cffffh sa172 64 kwords ac0000h?acffffh sa141 64 kwords 8d0000h?8dffffh sa173 64 kwords ad0000h?adffffh sa142 64 kwords 8e0000h?8effffh sa174 64 kwords ae0000h?aeffffh sa143 64 kwords 8f0000h?8fffffh sa175 64 kwords af0000h?afffffh bank 9 sa144 64 kwords 900000h?90ffffh bank 11 sa176 64 kwords b00000h?b0ffffh sa145 64 kwords 910000h?91ffffh sa177 64 kwords b10000h?b1ffffh sa146 64 kwords 920000h?92ffffh sa178 64 kwords b20000h?b2ffffh sa147 64 kwords 930000h?93ffffh sa179 64 kwords b30000h?b3ffffh sa148 64 kwords 940000h?94ffffh sa180 64 kwords b40000h?b4ffffh sa149 64 kwords 950000h?95ffffh sa181 64 kwords b50000h?b5ffffh sa150 64 kwords 960000h?96ffffh sa182 64 kwords b60000h?b6ffffh sa151 64 kwords 970000h?97ffffh sa183 64 kwords b70000h?b7ffffh sa152 64 kwords 980000h?98ffffh sa184 64 kwords b80000h?b8ffffh sa153 64 kwords 990000h?99ffffh sa185 64 kwords b90000h?b9ffffh sa154 64 kwords 9a0000h?9affffh sa186 64 kwords ba0000h?baffffh sa155 64 kwords 9b0000h?9bffffh sa187 64 kwords bb0000h?bbffffh sa156 64 kwords 9c0000h?9cffffh sa188 64 kwords bc0000h?bcffffh sa157 64 kwords 9d0000h?9dffffh sa189 64 kwords bd0000h?bdffffh sa158 64 kwords 9e0000h?9effffh sa190 64 kwords be0000h?beffffh sa159 64 kwords 9f0000h?9fffffh sa191 64 kwords bf0000h?bfffffh table 5.2 s29ns256p sector & memory address map (sheet 2 of 3) bank sector sector size address range bank sector sector size address range 24 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) bank 12 sa192 64 kwords c00000h?c0ffffh bank 14 sa224 64 k words e00000h?e0ffffh sa193 64 kwords c10000h?c1ffffh sa225 64 k words e10000h?e1ffffh sa194 64 kwords c20000h?c2ffffh sa226 64 k words e20000h?e2ffffh sa195 64 kwords c30000h?c3ffffh sa227 64 k words e30000h?e3ffffh sa196 64 kwords c40000h?c4ffffh sa228 64 k words e40000h?e4ffffh sa197 64 kwords c50000h?c5ffffh sa229 64 k words e50000h?e5ffffh sa198 64 kwords c60000h?c6ffffh sa230 64 k words e60000h?e6ffffh sa199 64 kwords c70000h?c7ffffh sa231 64 k words e70000h?e7ffffh sa200 64 kwords c80000h?c8ffffh sa232 64 k words e80000h?e8ffffh sa201 64 kwords c90000h?c9ffffh sa233 64 k words e90000h?e9ffffh sa202 64 kwords ca0000h?caffffh sa234 64 k words ea0000h?eaffffh sa203 64 kwords cb0000h?cbffffh sa235 64 k words eb0000h?ebffffh sa204 64 kwords cc0000h?ccffffh sa236 64 k words ec0000h?ecffffh sa205 64 kwords cd0000h?cdffffh sa237 64 k words ed0000h?edffffh sa206 64 kwords ce0000h?ceffffh sa238 64 k words ee0000h?eeffffh sa207 64 kwords cf0000h?cfffffh sa239 64 k words ef0000h?efffffh bank 13 sa208 64 kwords d00000h?d0ffffh bank 15 sa240 64 k words f00000h?f0ffffh sa209 64 kwords d10000h?d1ffffh sa241 64 k words f10000h?f1ffffh sa210 64 kwords d20000h?d2ffffh sa242 64 k words f20000h?f2ffffh sa211 64 kwords d30000h?d3ffffh sa243 64 k words f30000h?f3ffffh sa212 64 kwords d40000h?d4ffffh sa244 64 k words f40000h?f4ffffh sa213 64 kwords d50000h?d5ffffh sa245 64 k words f50000h?f5ffffh sa214 64 kwords d60000h?d6ffffh sa246 64 k words f60000h?f6ffffh sa215 64 kwords d70000h?d7ffffh sa247 64 k words f70000h?f7ffffh sa216 64 kwords d80000h?d8ffffh sa248 64 k words f80000h?f8ffffh sa217 64 kwords d90000h?d9ffffh sa249 64 k words f90000h?f9ffffh sa218 64 kwords da0000h?daffffh sa250 64 k words fa0000h?faffffh sa219 64 kwords db0000h?dbffffh sa251 64 k words fb0000h?fbffffh sa220 64 kwords dc0000h?dcffffh sa252 64 k words fc0000h?fcffffh sa221 64 kwords dd0000h?ddffffh sa253 64 k words fd0000h?fdffffh sa222 64 kwords de0000h?deffffh sa254 64 k words fe0000h?feffffh sa223 64 kwords df0000h?dfffffh sa255 16 k words ff0000h?ff3fffh sa256 16 k words ff4000h?ff7fffh sa257 16 k words ff8000h?ffbfffh sa258 16 k words ffc000h?ffffffh table 5.2 s29ns256p sector & memory address map (sheet 3 of 3) bank sector sector size address range bank sector sector size address range february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 25 data sheet (advance information) table 5.3 s29ns128p sector & memory address map (sheet 1 of 2) bank sector sector size address range bank sector sector size address range bank 0 sa0 64 kwords 000000h?00ffffh bank 4 sa32 64 kwords 200000h?20ffffh sa1 64 kwords 010000h?01ffffh sa33 64 kwords 210000h?21ffffh sa2 64 kwords 020000h?02ffffh sa34 64 kwords 220000h?22ffffh sa3 64 kwords 030000h?03ffffh sa35 64 kwords 230000h?23ffffh sa4 64 kwords 040000h?04ffffh sa36 64 kwords 240000h?24ffffh sa5 64 kwords 050000h?05ffffh sa37 64 kwords 250000h?25ffffh sa6 64 kwords 060000h?06ffffh sa38 64 kwords 260000h?26ffffh sa7 64 kwords 070000h?07ffffh sa39 64 kwords 270000h?27ffffh bank 1 sa8 64 kwords 080000h?08ffffh bank 5 sa40 64 kwords 280000h?28ffffh sa9 64 kwords 090000h?09ffffh sa41 64 kwords 290000h?29ffffh sa10 64 kwords 0a0000h?0affffh sa42 64 kwords 2a0000h?2affffh sa11 64 kwords 0b0000h?0bffffh sa43 64 kwords 2b0000h?2bffffh sa12 64 kwords 0c0000h?0cffffh sa44 64 kwords 2c0000h?2cffffh sa13 64 kwords 0d0000h?0dffffh sa45 64 kwords 2d0000h?2dffffh sa14 64 kwords 0e0000h?0effffh sa46 64 kwords 2e0000h?2effffh sa15 64 kwords 0f0000h?0fffffh sa47 64 kwords 2f0000h?2fffffh bank 2 sa16 64 kwords 100000h?10ffffh bank 6 sa48 64 kwords 300000h?30ffffh sa17 64 kwords 110000h?11ffffh sa49 64 kwords 310000h?31ffffh sa18 64 kwords 120000h?12ffffh sa50 64 kwords 320000h?32ffffh sa19 64 kwords 130000h?13ffffh sa51 64 kwords 330000h?33ffffh sa20 64 kwords 140000h?14ffffh sa52 64 kwords 340000h?34ffffh sa21 64 kwords 150000h?15ffffh sa53 64 kwords 350000h?35ffffh sa22 64 kwords 160000h?16ffffh sa54 64 kwords 360000h?36ffffh sa23 64 kwords 170000h?17ffffh sa55 64 kwords 370000h?37ffffh bank 3 sa24 64 kwords 180000h?18ffffh bank 7 sa56 64 kwords 380000h?38ffffh sa25 64 kwords 190000h?19ffffh sa57 64 kwords 390000h?39ffffh sa26 64 kwords 1a0000h?1affffh sa58 64 kwords 3a0000h?3affffh sa27 64 kwords 1b0000h?1bffffh sa59 64 kwords 3b0000h?3bffffh sa28 64 kwords 1c0000h?1cffffh sa60 64 kwords 3c0000h?3cffffh sa29 64 kwords 1d0000h?1dffffh sa61 64 kwords 3d0000h?3dffffh sa30 64 kwords 1e0000h?1effffh sa62 64 kwords 3e0000h?3effffh sa31 64 kwords 1f0000h?1fffffh sa63 64 kwords 3f0000h?3fffffh bank 8 sa64 64 kwords 400000h?40ffffh bank 12 sa96 64 k words 600000h?60ffffh sa65 64 kwords 410000h?41ffffh sa97 64 k words 610000h?61ffffh sa66 64 kwords 420000h?42ffffh sa98 64 k words 620000h?62ffffh sa67 64 kwords 430000h?43ffffh sa99 64 k words 630000h?63ffffh sa68 64 kwords 440000h?44ffffh sa100 64 k words 640000h?64ffffh sa69 64 kwords 450000h?45ffffh sa101 64 k words 650000h?65ffffh sa70 64 kwords 460000h?46ffffh sa102 64 k words 660000h?66ffffh sa71 64 kwords 470000h?47ffffh sa103 64 k words 670000h?67ffffh bank 9 sa72 64 kwords 480000h?48ffffh bank 13 sa104 64 k words 680000h?68ffffh sa73 64 kwords 490000h?49ffffh sa105 64 k words 690000h?69ffffh sa74 64 kwords 4a0000h?4affffh sa106 64 k words 6a0000h?6affffh sa75 64 kwords 4b0000h?4bffffh sa107 64 k words 6b0000h?6bffffh sa76 64 kwords 4c0000h?4cffffh sa108 64 k words 6c0000h?6cffffh sa77 64 kwords 4d0000h?4dffffh sa109 64 k words 6d0000h?6dffffh sa78 64 kwords 4e0000h?4effffh sa110 64 k words 6e0000h?6effffh sa79 64 kwords 4f0000h?4fffffh sa111 64 k words 6f0000h?6fffffh 26 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) bank 10 sa80 64 kwords 500000h?50ffffh bank 14 sa112 64 k words 700000h?70ffffh sa81 64 kwords 510000h?51ffffh sa113 64 k words 710000h?71ffffh sa82 64 kwords 520000h?52ffffh sa114 64 k words 720000h?72ffffh sa83 64 kwords 530000h?53ffffh sa115 64 k words 730000h?73ffffh sa84 64 kwords 540000h?54ffffh sa116 64 k words 740000h?74ffffh sa85 64 kwords 550000h?55ffffh sa117 64 k words 750000h?75ffffh sa86 64 kwords 560000h?56ffffh sa118 64 k words 760000h?76ffffh sa87 64 kwords 570000h?57ffffh sa119 64 k words 770000h?77ffffh bank 11 sa88 64 kwords 580000h?58ffffh bank 15 sa120 64 k words 780000h?78ffffh sa89 64 kwords 590000h?59ffffh sa121 64 k words 790000h?79ffffh sa90 64 kwords 5a0000h?5affffh sa122 64 k words 7a0000h?7affffh sa91 64 kwords 5b0000h?5bffffh sa123 64 k words 7b0000h?7bffffh sa92 64 kwords 5c0000h?5cffffh sa124 64 k words 7c0000h?7cffffh sa93 64 kwords 5d0000h?5dffffh sa125 64 k words 7d0000h?7dffffh sa94 64 kwords 5e0000h?5effffh sa126 64 k words 7e0000h?7effffh sa95 64 kwords 5f0000h?5fffffh sa127 16 k words 7f0000h?7f3fffh sa128 16 k words 7f4000h?7f7fffh sa129 16 k words 7f8000h?7fbfffh sa130 16 k words 7fc000h?7fffffh table 5.3 s29ns128p sector & memory address map (sheet 2 of 2) bank sector sector size address range bank sector sector size address range february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 27 data sheet (advance information) 6. device operations this section describes the read, pr ogram, erase, simultaneous read/writ e operations, handshaking, and reset features of the flash devices. operations are initiated by writing specific commands or a sequence with specific address and data patterns into the command registers (see tables 11.1 and 11.2 ). the command register itself does not occupy any addressable memory location; rather, it is composed of latches that store t he commands, along with the address and data information needed to execute the comman d. the contents of the r egister serve as input to the internal state machine and the st ate machine outputs dictate the functi on of the device. writing incorrect address and data values or writing them in an improper sequence may place the device in an unknown state, in which case the system must write the reset command to return the device to the reading array data mode. 6.1 device operation table the device must be setup appro priately for each operation. table 6.1 describes the required state of each control pin for any particular operation. legend l = logic 0, h = logic 1, x = can be either v il or v ih ., = rising edge, = high to low, = toggle. notes 1. address is latched on the rising edge of clock. 2. clk must stay low or high after ce# goes low when device in asynchronous read mode. 6.2 asynchronous read all memories require access time to output array data. in an asynchronous read operation, data is read from one memory location at a time. addresses are present ed to the device in random order, and the propagation delay through the device causes the data on its outputs to arrive asynchronously with the address on its inputs. to read data from the memory arra y, the system must first assert a valid address whil e driving avd# and ce# to v il . we# must remain at v ih . the rising edge of avd# latches the address. the oe# signal must be driven to v il , once avd# has been driven to v ih . the data is output on a/dq15 ? a/dq 0 pins after the access time (t oe ) has elapsed from the falling edge of oe#. table 6.1 device operations operation ce# oe# we# clk avd# amax? a16 a/dq15? a/dq0 rdy reset# asynchronous read ? addresses latched l l h x addr in i/o h h asynchronous write l h x addr in i/o h h standby (ce#) h x x x x x high z high z h hardware reset x x x x x x high z high z burst read operations latch starting burst address by clk l h h l addr in addr in x h advance burst read to next address l l h h x i/o h h terminate current burst read cycle h x h x x x high z high z h terminate current burst read cycle via reset# x x h x x x high z high z l terminate current burst read cycle and start new burst read cycle l x h addr in addr in x h 28 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) 6.3 synchronous (burst) read operation the device is capable of continuous sequential burst operation and linear bu rst operation of a preset length. when the device first powers up, it is enabled for asynchronous read and can be automatically enabled for burst mode and the address is latched on the first risi ng edge of clk input, while avd# is held low for one clock cycle. prior to activating the clock signal, the system should determine how many wait states are desired for the initial word (t iacc ) of each burst access, what mode of burst operation is desired and how the rdy signal transitions with valid data. the system would then write the configuration re gister command sequence. at startup the syst em writes the set configuration register command sequence to optimize the system performance. the data is output t iacc after the rising edge of the first clk. subs equent words are output t bacc after the rising edge of each successive clock cycle, which automatically increments the internal address counter. note that data is output only at the rising edge of the clock. rdy indicates the initial latency. note that the device has a fixed internal address boundary that occurs every 128 words. no boundary crossing latency is required when the device o perates with wait states set from 2 to 9. 6.3.1 latency tables for variable wait state ta b l e s 6 . 2 ? 6.9 show the latency for variable wait state in a normal burst operation. table 6.2 address latency for 9 wait states word initial wait 0 9 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1d2d3d4d5d6d7 1 ws d8 2 d2d3d4d5d6d7 1 ws 1 ws d8 3 d3d4d5d6d7 1 ws 1 ws 1 ws d8 4d4d5d6d7 1 ws 1 ws 1 ws 1 ws d8 5d5d6d7 1 ws 1 ws 1 ws 1 ws 1 ws d8 6d6d7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws d8 7d7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws d8 table 6.3 address latency for 8 wait states word initial wait 0 8 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1d2d3d4d5d6d7d8d9 2 d2d3d4d5d6d7 1 ws d8 d9 3 d3d4d5d6d7 1 ws 1 ws d8 d9 4d4d5d6d7 1 ws 1 ws 1 ws d8 d9 5d5d6d7 1 ws 1 ws 1 ws 1 ws d8 d9 6d6d7 1 ws 1 ws 1 ws 1 ws 1 ws d8 d9 7d7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws d8 d9 february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 29 data sheet (advance information) table 6.4 address latency for 7 wait states word initial wait 0 7 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1d2d3d4d5d6d7d8d9 2 d2d3d4d5d6d7d8d9d10 3 d3d4d5d6d7 1 ws d8 d9 d10 4d4d5d6d7 1 ws 1 ws d8 d9 d10 5d5d6d7 1 ws 1 ws 1 ws d8 d9 d10 6d6d7 1 ws 1 ws 1 ws 1 ws d8 d9 d10 7d7 1 ws 1 ws 1 ws 1 ws 1 ws d8 d9 d10 table 6.5 address latency for 6 wait states word initial wait 0 6 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1d2d3d4d5d6d7d8d9 2 d2d3d4d5d6d7d8d9d10 3 d3d4d5d6d7d8d9d10d11 4d4d5d6d7 1 ws d8 d9 d10 d11 5d5d6d7 1 ws 1 ws d8 d9 d10 d11 6d6d7 1 ws 1 ws 1 ws d8 d9 d10 d11 7d7 1 ws 1 ws 1 ws 1 ws d8 d9 d10 d11 table 6.6 address latency for 5 wait states word initial wait 0 5 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1d2 d3 d4d5d6d7d8d9 2d2d3d4d5d6d7d8d9d10 3d3d4d5d6d7d8d9d10d11 4 d4 d5 d6 d7 d8 d9 d10 d11 d12 5d5d6d7 1 ws d8 d9 d10 d11 d12 6d6d7 1 ws 1 ws d8 d9 d10 d11 d12 7d7 1 ws 1 ws 1 ws d8 d9 d10 d11 d12 table 6.7 address latency for 4 wait states word initial wait 0 4 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1d2 d3d4d5d6d7d8d9 2 d2d3 d4d5d6d7d8d9d10 3d3d4d5d6d7d8d9d10d11 4 d4 d5 d6 d7 d8 d9 d10 d11 d12 5 d5 d6 d7 d8 d9 d10 d11 d12 d13 6d6d7 1 ws d8 d9 d10 d11 d12 d13 7d7 1 ws 1 ws d8 d9 d10 d11 d12 d13 30 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) table 6.8 address latency for 3 wait states word initial wait 0 3 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1d2d3d4d5 d6 d7 d8 d9 2 d2d3d4d5d6 d7 d8 d9d10 3 d3d4d5d6d7 d8 d9d10d11 4 d4d5d6d7d8 d9d10d11d12 5 d5d6d7d8d9d10d11d12d13 6 d6 d7 d8 d9 d10 d11 d12 d13 d14 7d7 1 ws d8 d9 d10 d11 d12 d13 d14 table 6.9 address latency for 2 wait states word initial wait 0 2 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1d2d3d4d5d6d7d8d9 2 d2d3d4d5d6d7d8d9d10 3 d3d4d5d6d7d8d9d10d11 4 d4d5d6 d7 d8 d9 d10 d11 d12 5 d5d6d7 d8 d9 d10 d11 d12 d13 6 d6d7d8 d9 d10 d11 d12 d13 d14 7 d7 d8 d9 d10 d11 d12 d13 d14 d15 february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 31 data sheet (advance information) figure 6.1 synchronous read flow chart 6.3.2 continuous burst read mode in the continuous burst read mode, the device output s sequential burst data from the starting address given and then wraps around to address 000000h when it reac hes the highest addressable memory location. the burst read mode continues until the system drives ce# high, or reset= v il . continuous burst mode can also be aborted by asserting avd# low and providing a new address to the device. if the address being read crosses a 128-word line bounda ry within the same bank, but not into a program or erase suspended sector, as mentioned above, addition al latency cycles are required as reflected by the configuration register table ( table 6.11 ) and ta bl e s 6 . 2 ? 6.9 . if the address crosses a bank boundary while the subsequent bank is programming or erasing, the device provides read status information and the clock is ignored. upon completion of status read or program or erase operation, the host can restart a burst read operation using a new address and avd# pulse. write unlock cycles: address 555h, data aah address 2aah, data 55h set configuration registers command and settings: address 555h, data d0h address x00h, data cr0-cr1 load initial address address = ra read initial data rd = dq[15:0] read next data rd = dq[15:0] wait t iacc + programmable wait state setting wait x clocks: additional latency due to starting address, clock frequency, and boundary crossing end of data? yes crossing boundary? no yes completed delay x clocks unlock cycle 1 unlock cycle 2 ra = read address rd = read data command cycle cr = configuration registers cr13-cr11 sets initial access time (from address latched to valid data) from 2 to 7 clock cycles note: setup configuration register parameters refer to the latency tables. 32 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) 6.3.3 8-word, 16-word, and 32-word linear burst read with wrap around in a linear burst read operation, a fixed number of words (8, 16, or 32 words) are read from consecutive addresses that are determined by the group within wh ich the starting address falls. the groups are sized according to the number of words read in a single burst sequence for a given mode (see table 6.10 ). for example, if the starting address in the 8-word mode is 3ch, the address range to be read is 38-3fh, and the burst sequence is 3c-3d-3e-3f-38-39-3a-3bh. thus, the device outputs all words in that burst address group until all word are read, regardless of where t he starting address occurs in the address group, and then terminates the burst read. in a similar fashion, the 16-word and 32-word linear wrap modes begin their burst sequence on the starting address provided to the device, then wrap back to the first address in the selected address group. note that in this mode the address pointer does not cr oss the boundary that occurs every 128 words; thus, no additional wait states are in serted due to boundary crossing. 6.3.4 8-word, 16-word, and 32-wo rd linear burst without wrap around if wrap around is not enabled for linear burst read operat ions, the 8-word, 16-word, or 32-word burst executes up to the maximum memory address of the selected num ber of words. the burst stops after 8, 16, or 32 addresses and does not wrap around to the first address of the selected group. for example, if the starting address in the 8-word mode is 3ch, the address range to be read is 3c-43h, and the burst sequence is 3c-3d-3e-3f-40-41-42-43h if wr ap around is not enabled. the next address to be read requires a new address and avd# pulse. note that in th is burst read mode, the address pointer may cross the boundary that occurs every 128 words, which incu rs the additional boundary crossing wait state. 6.3.5 configuration registers this device uses two 16-bit config uration registers to set various operational parameters. upon power-up or hardware reset, the device is capable of the asynchronous read mode and synchronous read, and the configuration register settings are in their default state. the host system should determine the proper settings for the entire configuration register, and then exec ute the set configuration register command sequence before attempting burst operations. the configuration register can also be read using a command sequence (see table 11.1 ). the following list describes the register settings. table 6.10 burst address groups mode group size group address ranges 8-word 8 words 0 ? 7h, 8 ? fh, 10 ? 17h,... 16-word 16 words 0 ? fh, 10 ? 1fh, 20 ? 2fh,... 32-word 32 words 00?1fh, 20?3fh, 40?5fh,... table 6.11 configuration register cr bit function settings (binary) cr0.15 reserved (not used) 0 = reserved (default) 1 = reserved cr0.14 reserved (not used) 0 = reserved (default) 1 = reserved february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 33 data sheet (advance information) notes 1. the addresses are latched by rising edge of clk. 2. cr1.0 to cr1.3 and cr1.5 to cr1.15 = 1 (default). 3. a software reset command is required after read command. 4. cr0.3 is ignored if in continuous read mode (no wrap around). 6.4 autoselect the autoselect is used for manufactur er id, device identification, and sector protection information. this mode is primarily intended for programming equipment to automatically match a device with its corresponding programming algorithm. the autose lect codes can also be accessed in the system. when verifying sector protection, the sector address must appear on t he appropriate highest order address bits (see table 6.12 ). the remaining address bits are don't care. the most signifi cant four bits of the address during the third write cycle select the bank from which th e autoselect codes are read by t he host. all other banks can be accessed normally for data read without exiting the autoselect mode. cr1.0 programmable wait state (note 1) 0000 = initial data is valid on the 2nd rising clk edge avd# transition to v ih 0001 3rd cr0.13 0010 4th 0011 5th cr0.12 0100 6th 0101 7th cr0.11 0110 = reserved 0111 1000 = initial data is valid on the 8th rising clk edge avd# transition to v ih 1001 9th ? 1101 = initial data is valid on the 13th rising clk edge avd# transition to v ih (default) 1110 = reserved 1111 cr0.10 rdy polarity 0 = rdy signal is active low 1 = rdy signal is active high (default) cr0.9 reserved (not used) 0 = reserved 1 = reserved (default) cr0.8 rdy 0 = rdy active one clock cycle before data 1 = rdy active with data (default) cr0.7 reserved (not used) 0 = reserved 1 = reserved (default) cr0.6 reserved (not used) 0 = reserved 1 = reserved (default) cr0.5 reserved (not used) 0 = reserved (default) 1 = reserved cr1.4 output drive strength 0 = full drive= current driver strength (default) 1 = half drive cr0.4 rdy function 0 = rdy (default) 1 = reserved cr0.3 burst wrap around 0 = no wrap around burst 1 = wrap around burst (default) cr0.2 burst length 000 = continuous (default) 010 = 8-word linear burst cr0.1 011 = 16-word linear burst cr0.0 100 = 32-word linear burst (all other bit settings are reserved) table 6.11 configuration register cr bit function settings (binary) 34 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) ? to access the autoselect codes, the host system must issue the autoselect command. ? the autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. ? the autoselect command may not be written while the device is actively programming or erasing. autoselect does not support simultaneous operations or burst mode. ? the system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in erase suspend). see table 11.1 for command sequence details. software functions and sample code notes 1. any offset within the device works. 2. ba = bank address. the bank address is required. 3. base = base address. the following is a c source code example of using the autoselect function to read the manufacturer id. refer to the spansion low level driver user?s guide (available on www.spansion.com ) for general information on spansion flash memory software development guidelines. table 6.12 autoselect addresses description address read data manufacturer id byte 00 (ba) + 00h 0001h device id, byte 01 (ba) + 01h 307eh(ns512p) 317eh(ns256p) 327eh(ns128p) sector lock/unlock byte 02 (sa) + 02h 0001h = locked, 0000h = unlocked indicator bits byte 07 (ba) + 07h dq15?dq8 = reserved dq7 ? factory lock bit; 1 = locked, 0 = not locked dq6 ? customer lock bit; 1 = locked, 0 = not locked dq5 ? handshake bit; 1 = reserved, 0 = standard handshake dq4 and dq3 ? wp# protection boot code; 01 = wp# protects top boot sectors, dq2?dq0 = reserved device id, byte 0e (ba) + 0eh 303fh (ns512p) 3141h (ns256p) 3243h (ns128p) device id, byte 0f (ba) + 0fh 3000h (ns512p) 3100h (ns256p) 3200h (ns128p) table 6.13 autoselect entry (lld function = lld_autoselectentrycmd) cycle operation byte address word address data unlock cycle 1 write ba+aaah ba+555h 0x00aah unlock cycle 2 write ba+555h ba+2aah 0x0055h autoselect command write ba+aaah ba+555h 0x0090h table 6.14 autoselect exit (lld function = lld_autoselectexitcmd) cycle operation byte address word address data unlock cycle 1 write base + xxxxh base + xxxxh 0x00f0h february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 35 data sheet (advance information) /* here is an example of autoselect mode (getting manufacturer id) */ /* define uint16 example: typedef unsigned short uint16; */ uint16 manuf_id; /* auto select entry */ *( (uint16 *)bank_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)bank_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)bank_addr + 0x555 ) = 0x0090; /* write autoselect command */ /* multiple reads can be performed after entry */ manuf_id = *( (uint16 *)bank_addr + 0x000 ); /* read manuf. id */ /* autoselect exit */ *( (uint16 *)base_addr + 0x000 ) = 0x00f0; /* exit autoselect (write reset command) */ 6.5 program/erase operations these devices are capable of several modes of progra mming and or erase operations which are described in detail in the following sections. however, prior to any programming and or erase operation, devices can be setup appropriately as outlined in the configuration register ( table 6.11 ). for any program and or erase operations, including writing command sequences, the system must drive avd# and ce# to v il , and oe# to v ih when providing an address to the device, and drive we# and ce# to v il , and oe# to v ih when writing commands or programming data. all addresses are latched on the rising edge of avd# or falling edge of we#, and all data is latched on the first rising edge of we#. note the following: ? when the embedded program/erase algorithm is complete, the device returns to the read mode. ? the system can determine the status of the program/er ase operation. refer to t he write operation status section for further information. ? while 1 can be programmed to 0 , a 0 cannot be programmed to a 1 . any such attempt is ignored as only an erase operation can covert a 0 to a 1 . ? any commands written to the device during the embedded program/erase algorithm are ignored except the program/erase suspend command. ? secured silicon sector, autoselect, and cfi functions are unavailable when a program operation is in progress. ? a hardware reset or power removal immediately termi nates the program/erase op eration and the program/ erase command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. ? programming is allowed in any sequence and across sector boundaries only for single word programming operation. see write buffer programming when using the write buffer. note: the system may also lock or unlock any sector while the erase operation is suspended. 6.5.1 single word programming single word programming mode is the simplest met hod of programming. in this mode, four flash command write cycles are used to program an individual flash ad dress. while the single wo rd programming method is supported by all spansion devices, in general it is not recommended for devices that support write buffer programming. see table 11.1 for the requir ed bus cycles and figure 6.2 for the flowchart. 36 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) when the embedded program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. the system can determine the status of the prog ram operation by using dq7 or dq6. refer to the write operation status section for in formation on these status bits. figure 6.2 single word program software functions and sample code note base = base address. the following is a c source code example of using the single word program function. refer to the spansion low level driver user?s guide (available on www.spansion.com ) for general information on spansion flash memory software development guidelines. table 6.15 single word program (lld function = lld_programcmd) cycle operation byte address word address data unlock cycle 1 write base + aaah base + 555h 00aah unlock cycle 2 write base + 554h base + 2aah 0055h program setup write base + aaah base + 555h 00a0h program write word address word address data word write unlock cycles: address 555h, data aah address 2aah, data 55h write program command: address 555h, data a0h program data to address: pa, pd unlock cycle 1 unlock cycle 2 setup command program address (pa), program data (pd) operation failed perform polling algorithm (see write operation status flowchart) yes yes no no polling status = busy? polling status = complete? error condition (exceeded timing limits) operation successfully completed february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 37 data sheet (advance information) /* example: program command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x00a0; /* write program setup command */ *( (uint16 *)pa ) = data; /* write data to be programmed */ /* poll for program completion */ 6.5.2 write buffer programming write buffer programming allows the system to write a maximum of 32 wo rds in one programming operation. this results in a faster effective wo rd programming time than the standard word programming algorithms. the write buffer programming command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the write buffer lo ad command written at the sector address in which programming occurs. at this point , the system writes the number of word locations minus 1 that is loaded into the page buffer at the sector address in which prog ramming occurs. this tells the device how many write buffer addresses will be loaded with data and therefore when to expect the program buffer to flash confirm command. the number of locations to program cannot exceed the size of the write buffer or the operation aborts. (note: the size of the write buffer is depende nt upon which data are being loaded. also note that the number loaded = the number of locations to program mi nus 1. for example, if the system programs 6 address locations, then 05h should be written to the device.) the system then writes the starting address/data combination. this starti ng address is the first address/data pair to be programmed, and selects the write-buffer-page address. all subsequent address/data pairs must be in sequential order. the write-buffer addresses must be in the same sector for a ll address/data pairs loaded into the write buffer. it is to be noted that write buffer programming ca nnot be performed across multip le sectors. if the system attempts to load programming data outside of the selected write-buffer addresses, the operation aborts after the write to buffer command is executed. also, the st arting address must be the least significant address and must be incremental and that the write buffer data cannot be in different sectors. after writing the starting address/data pair, the system then writes the remaining address/data pairs into the write buffer. write buffer locations must be loaded in sequential order starting with the lowest address in the page. note that if the number of a ddress/data pairs do not match the word count, the program buffer to flash command is ignored. note that if a write buffer address lo cation is loaded multiple times, the address/data pair counter decrements for every data load operation. also, the last data loaded at a location before the program buffer to flash confirm command is programmed into the device. it is the software?s responsibility to comprehend ramifications of loading a write-buffer location mo re than once. the counter decrements for each data load operation, not for each unique write-buffer-address location. once the specified number of writ e buffer locations have been load ed, the system must then write the program buffer to flash command at the sector address. any ot her address/data write combinations abort the write buffer programming operation. the device then goes busy . the data bar polling techniques should be used while monitoring the last address location loaded into the write buffer. this eliminates the need to store an address in memory because the system can load the last address location, issue the program confirm command at the last loaded address location , and then data bar poll at that same address. dq7, dq6, dq5, dq2, and dq1 should be monitored to determine the devic e status during write buffer programming. the write-buffer embedded programming operation can be suspende d using the standard suspend/resume commands. upon successful completion of the write buff er programming operation, the device returns to read mode. the write buffer programming sequenc e is aborted in the following ways: ? load a value that is greater than the buffer size during the number of locations to program step (dq7 is not valid in this condition). ? write to an address in a sector different than the one specified during the write-buffer-load command. ? write an address/data pair to a different writ e-buffer-page than the one selected by the starting address during the write buffer data loading stage of the operation. ? write data other than the confirm command after the specified number of data load cycles. 38 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) software functions and sample code notes 1. base = base address. 2. last = last cycle of write buffer program operation; depend ing on number of words written, the total number of cycles may be from 6 to 37. 3. for maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (n words) possible . the following is a c source code example of using the write buffer program function. refer to the spansion low level driver user?s guide ( www.spansion.com ) for general information on spansion flash memory software development guidelines. /* example: write buffer programming command */ /* notes: write buffer programming limited to 16 words. */ /* all addresses to be written to the flash in */ /* one operation must be within the same write buffer. */ /* a write buffer begins at addresses evenly divisible */ /* by 0x20. uint16 i; */ uint16 *src = source_of_data; /* address of source data */ uint16 *dst = destination_of_data; /* flash destination address */ uint16 wc = words_to_program -1; /* word count (minus 1) */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)dst ) = 0x0025; /* write write buffer load command */ *( (uint16 *)dst ) = wc; /* write word count (minus 1) */ for (i=0;i<=wc;i++) { *dst++ = *src++; /* all dst must be in same write buffer */ } *( (uint16 *)sector_address ) = 0x0029; /* write confirm command */ /* poll for completion */ /* example: write buffer abort reset */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x00f0; /* write buffer abort reset */ table 6.16 write buffer program (lld functions used = lld_writetobuffercmd, lld_programbuffertoflashcmd) cycle description operation byte address word address data 1 unlock write base + aaah base + 555h 00aah 2 unlock write base + 554h base + 2aah 0055h 3 write buffer load command write program address 0025h 4 write word count write program address word count (n?1)h number of words (n) loaded into the write buffer can be from 1 to 32 words. 5 to 36 load buffer word n write program address, word n word n last write buffer to flash write sector address 0029h february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 39 data sheet (advance information) figure 6.3 write buffer programming operation 6.5.3 sector erase the sector erase function erases one or more sectors in the memory array. (see table 11.1 and figure 6.4 .) the device does not require the system to preprog ram prior to erase. the embedded erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. after a successful sector er ase, all locations within the erased sector contain ffffh. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of no less than t sea occurs. during the time- out period, additional sector addresse s and sector erase commands may be written. loading the sector erase buffer may be done in any sequence, and the number of se ctors may be from one sector to all sectors. the time between these additional cycles must be less than t sea . any sector erase address and command following the exceeded time-out (t sea ) may or may not be accepted. any command other than sector erase or erase suspend during the time-out period resets th at bank to the read mode. t he system can monitor dq3 write unlock cycles: address 555h, data aah address 2aah, data 55h issue write buffer load command: program address data 25h load word count to program program data to address: sa = wc unlock cycle 1 unlock cycle 2 wc = number of words ? 1 yes yes yes yes no no no no wc = 0? write buffer abort? polling status = done? error? fail. issue reset command to return to read array mode. pass. device is in read mode. confirm command: sa 29h perform polling algorithm (see write operation status flowchart) write next word, decrement wc: pa data , wc = wc ? 1 reset. issue write buffer abort reset command 40 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) to determine if the sector erase timer has timed out (see the section, dq3: sector erase timeout state indicator .) the time-out begins from the rising edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. note that while the embedded erase operation is in progress, the system can read data from the non-erasing banks. the system can determine t he status of the erase ope ration by reading dq7 or dq6/dq2 in the erasing bank. refer to write operation status for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset imme diately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. figure 6.4 illustrates the algorithm for the erase operation. refer to program/erase operations for parameters and timing diagrams. software functions and sample code the following is a c source code example of us ing the sector erase function. refer to the spansion low level driver user?s guide (available on www.spansion.com ) for general information on spansion flash memory software development guidelines. /* example: sector erase command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0080; /* write setup command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write additional unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write additional unlock cycle 2 */ *( (uint16 *)sector_address ) = 0x0030; /* write sector erase command */ table 6.17 sector erase (lld function = lld_sectorerasecmd) cycle description operation byte address word address data 1 unlock write base + aaah base + 555h 00aah 2 unlock write base + 554h base + 2aah 0055h 3 setup command write base + aaah base + 555h 0080h 4 unlock write base + aaah base + 555h 00aah 5 unlock write base + 554h base + 2aah 0055h 6 sector erase command write sector address sector address 0030h unlimited additional sectors may be selected for erase; command(s) must be written within t sea . february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 41 data sheet (advance information) figure 6.4 sector erase operation notes 1. see table 11.1 for erase command sequence. 2. see dq3: sector erase timeout state indicator for information on the sector erase timeout. 6.5.4 chip erase command sequence chip erase is a six-bus cycle operation as indicated by table 11.1 . these commands invoke the embedded erase algorithm, which does not require the system to preprogram prior to erase. the embedded erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. after a successful chip erase, all lo cations of the chip contain ffffh. the system is not required to provide any controls or timings during these operations. table 11.1 shows the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. the system ca n determine the status of the erase operation by usi ng dq7 or dq6/dq2. refer to the write operation status section for information on these status bits. no write unlock cycles: address 555h, data aah address 2aah, data 55h write sector erase cycles: address 555h, data 80h address 555h, data aah address 2aah, data 55h sector address, data 30h write additional sector addresses fail. write reset command to return to reading array. pass. device returns to reading array. perform write operation status algorithm select additional sectors? unlock cycle 1 unlock cycle 2 yes yes yes yes yes no no no no last sector selected? done? dq5 = 1? command cycle 1 command cycle 2 command cycle 3 specify first sector for erasure error condition (exceeded timing limits) status may be obtained by reading dq7, dq6 and/or dq2. poll dq3. dq3 = 1? ? each additional cycle must be written within t sea timeout ? timeout resets after each additional cycle is written ? the host system may monitor dq3 or wait t sea to ensure acceptance of erase commands ? no limit on number of sectors ? commands other than erase suspend or selecting additional sectors for erasure during timeout reset device to reading array data 42 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) any commands written during the chip erase operati on are ignored. however, note that a hardware reset immediately terminates the erase operation. if that o ccurs, the chip erase command sequence should be reinitiated once that bank has returned to read ing array data, to ens ure data integrity. software functions and sample code the following is a c source code example of us ing the chip erase function. refer to the spansion low level driver user?s guide ( www.spansion.com m) for general information on spansion flash memory software development guidelines. /* example: chip erase command */ /* note: cannot be suspended */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0080; /* write setup command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write additional unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write additional unlock cycle 2 */ *( (uint16 *)base_addr + 0x000 ) = 0x0010; /* write chip erase command */ 6.5.5 erase suspend/erase resume commands when the erase suspend command is written during t he sector erase time-out, the device immediately terminates the time-out period and suspends the er ase operation. the erase suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. the bank address is required w hen writing this command. this command is valid only during the sector erase operation, including the minimum t sea time-out period during the sector erase command sequence. the erase suspend command is igno red if written during the chip erase operation. when the erase suspend command is written after the t sea time-out period has expired and during the sector erase operation, the device requires a maximum of t esl (erase suspend latency) to suspend the erase operation. after the erase operation has been suspended, the ba nk enters the erase-suspend-read mode. the system can read data from or program data to any sector not selected for erasure. (the device erase suspends all sectors selected for erasure.) reading at any addre ss within erase-suspended se ctors produces status information on dq7-dq0. th e system can use dq7, or dq6, and dq2 t ogether, to determine if a sector is actively erasing or is erase-suspended. refer to table 6.27 for information on these status bits. after an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. the system can determine the status of the program operation using the dq 7 or dq6 status bits, just as in the standard program operation. in the erase-susp end-read mode, t he system can also issue the autosele ct command sequenc e. refer to the write buffer programming section and the autoselect section for details. to resume the sector erase operation, the syst em must write the erase resume command. the bank address of the erase-suspended bank is required when wr iting this command. furthe r writes of the resume command are ignored. another erase su spend command can be written afte r the chip has resumed erasing. note: while an erase operation can be suspended and re sumed multiple times, a minimum delay of t ers (erase resume to suspend) is required from resume to the next suspend. table 6.18 chip erase (lld function = lld_chiperasecmd) cycle description operation byte address word address data 1 unlock write base + aaah base + 555h 00aah 2 unlock write base + 554h base + 2aah 0055h 3 setup command write base + aaah base + 555h 0080h 4 unlock write base + aaah base + 555h 00aah 5 unlock write base + 554h base + 2aah 0055h 6 chip erase command write base + aaah base + 555h 0010h february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 43 data sheet (advance information) software functions and sample code the following is a c source code example of us ing the erase suspend function. refer to the spansion low level driver user?s guide ( www.spansion.com ) for general information on spansion flash memory software development guidelines. /* example: erase suspend command */ *( (uint16 *)bank_addr + 0x000 ) = 0x00b0; /* write suspend command */ the following is a c source code example of us ing the erase resume function. refer to the spansion low level driver user?s guide ( www.spansion.com ) for general information on spansion flash memory software development guidelines. /* example: erase resume command */ *( (uint16 *)bank_addr + 0x000 ) = 0x0030; /* write resume command */ /* the flash needs adequate time in the resume state */ 6.5.6 program suspend/p rogram resume commands the program suspend command allows the system to interrupt an embedded programming operation or a write to buffer programming operation so that data can read from any non-suspended sector. when the program suspend command is written during a progra mming process, the device halts the programming operation within t psl (program suspend latency) and updat es the status bits. addresses are don't-cares when writing the program suspend command. after the programming operation has been suspended, the system can read array data from any non- suspended sector. the program suspend command may also be issued during a programming operation while an erase is suspended. in this case, data may be read from any addresses not in erase suspend or program suspend. if a read is needed from the secured silicon sector area, then us er must use the proper command sequences to enter and exit this region. the system may also write the autoselect command sequence when the device is in program suspend mode. the device allows reading autoselect codes in the suspended sectors, since the codes are not stored in the memory array. when the device exits the auto select mode, the device reverts to program suspend mode, and is ready for another valid operation. see the autoselect section for more information. after the program resume command is written, th e device reverts to prog ramming. the system can determine the status of the program operation using the dq7 or dq6 stat us bits, just as in the standard program operation. see the write operation status section for more information. the system must write the program resume command (address bits are don't care ) to exit the program suspend mode and continue the programming operation. further writes of the program resume command are ignored. another program suspend command can be written after the device has resumed programming. note: while a program operation can be suspended and resumed multiple times, a minimum delay of t prs (program resume to suspend) is requir ed from resume to the next suspend. software functions and sample code table 6.19 erase suspend (lld function = lld_erasesuspendcmd) cycle operation byte address word address data 1 write bank address bank address 00b0h table 6.20 erase resume (lld function = lld_eraseresumecmd) cycle operation byte address word address data 1 write bank address bank address 0030h table 6.21 program suspend (lld function = lld_programsuspendcmd) cycle operation byte address word address data 1 write bank address bank address 00b0h 44 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) the following is a c source code example of usin g the program suspend function. refer to the spansion low level driver user?s guide ( www.spansion.com ) for general information on spansion flash memory software development guidelines. /* example: program suspend command */ *( (uint16 *)base_addr + 0x000 ) = 0x00b0; /* write suspend command */ the following is a c source code example of usi ng the program resume function. refer to the spansion low level driver user?s guide ( www.spansion.com ) for general information on spansion flash memory software development guidelines. /* example: program resume command */ *( (uint16 *)base_addr + 0x000 ) = 0x0030; /* write resume command */ 6.5.7 accelerated program/sector erase accelerated single word programming, write buffer pr ogramming and sector erase, operations are enabled through the v pp function. this method is faster than the standard chip program and erase command sequences. the accelerated ch ip program and erase functions must not be used more than 100 times per sector. in addition, accelerated chip program and erase should be performed at room temperature (30c 10c). if the system asserts v hh on this input, the device automatically enters the accelerated mode and uses the higher voltage on the input to reduce the time requi red for program and erase operations. the system can then use the write buffer load command sequence prov ided by the unlock bypass mode. note that if a write-to-buffer-abort reset is required while in unlock bypass mode, the full 3-cycle reset command sequence must be used to reset the device. removing v hh from the v pp input, upon completion of the embedded program or erase operation, returns the device to normal operation. ? sectors must be unlocked prior to raising v pp to v hh . ? the v pp pin must not be at v hh for operations other than accelerated programming and accelerated sector erase, or device damage may result. ? the v pp pin must not be left floating or unconnected; incons istent behavior of the device may result. ? v pp locks all sector if set to v il ; v pp should be set to v ih for all other conditions. 6.5.8 unlock bypass the unlock bypass feature allows the system to primarily program to a ban k faster than using the standard program command sequence. the unlock bypass command s equence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock by pass command, 20h. the device then enters the unlock bypass mode. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initia l two unlock cycles required in the standard program command sequence, resulting in faster total programmi ng time. the host system may also initiate the chip erase and sector erase sequences in the unlock by pass mode. the erase command sequences are four cycles in length instead of six cycles. table 11.1 shows the requirements for the unlock bypass command sequences. during the unlock bypass mode, only the read, unlo ck bypass program, unlock bypass sector erase, unlock bypass chip erase, and unlock bypass reset comm ands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass re set command sequence. the first cycle must contain table 6.22 program resume (lld function = lld_programresumecmd) cycle operation byte address word address data 1 write bank address bank address 0030h february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 45 data sheet (advance information) the bank address and the data 90h. the second cycle n eed only contain the data 00h. the bank then returns to the read mode. the device offers accelerated program operations through the v pp input. when the system asserts v hh on this input, the device automatically enters the unlock bypa ss mode. the system may then write the two-cycle unlock bypass program command sequence. the device uses the higher voltage on the v pp input to accelerate the operation. refer to the erase/program timing section for parameters, and figures 10.12 and 10.13 for timing diagrams software functions and sample code the following are c source code examples of using t he unlock bypass entry, program, and exit functions. refer to the spansion low level driver user?s guide ( www.spansion.com ) for general information on spansion flash memory software development guidelines. /* example: unlock bypass entry command */ *( (uint16 *)bank_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)bank_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)bank_addr + 0x555 ) = 0x0020; /* write unlock bypass command */ /* at this point, programming only takes two write cycles. */ /* once you enter unlock bypass mode, do a series of like */ /* operations (programming or sector erase) and then exit */ /* unlock bypass mode before beginning a different type of */ /* operations. */ /* example: unlock bypass program command */ /* do while in unlock bypass entry mode! */ *( (uint16 *)bank_addr + 0x555 ) = 0x00a0; /* write program setup command */ *( (uint16 *)pa ) = data; /* write data to be programmed */ /* poll until done or error. */ /* if done and more to program, */ /* do above two cycles again. */ /* example: unlock bypass exit command */ *( (uint16 *)base_addr + 0x000 ) = 0x0090; *( (uint16 *)base_addr + 0x000 ) = 0x0000; table 6.23 unlock bypass entry (lld function = lld_u nlockbypassentrycmd) cycle description operation byte address word address data 1 unlock write base + aaah base + 555h 00aah 2 unlock write base + 554h base + 2aah 0055h 3 entry command write base + aaah base + 555h 0020h table 6.24 unlock bypass program (lld function = lld_unlockbypassprogramcmd) cycle description operation byte address word address data 1 program setup command write base + xxxh base +xxxh 00a0h 2 program command write program address program address program data table 6.25 unlock bypass reset (lld function = lld_unlockbypassresetcmd) cycle description operation byte address word address data 1 reset cycle 1 write base + xxxh base +xxxh 0090h 2 reset cycle 2 write base + xxxh base +xxxh 0000h 46 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) 6.5.9 write oper ation status the device provides several bits to determine the st atus of a program or erase operation. the following subsections describe the function of dq1, dq2, dq3, dq5, dq6, and dq7. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether a bank is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the co mmand sequence. note that the data# polling is valid only for the last word being programmed in the writ e-buffer-page during write buffer programming. reading data# polling status on any word other than the last word to be programmed in the write-buffer-page returns false status information. similarly, attempting to program 1 over a 0 does not return vali d date# information. during the embedded program algorithm, the devic e outputs on dq7 the co mplement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. the system must provide the program address to read valid status in formation on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for approximately t psp , then that bank returns to the read mode. during the embedded erase algorithm, data# polling produces a 0 on dq7. when the embedded erase algorithm is complete, or if the bank enters the erase suspend mode, data# polling produces a 1 on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all se ctors selected for erasing are protected, data# polling on dq7 is active for approximately t asp , then the bank returns to the read m ode. if not all selected sectors are protected, the embedded eras e algorithm erases the unpr otected sectors, and ignores the selected sectors that are protected. however, if th e system reads dq7 at an address withi n a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq6-dq1 while output enable (oe# ) is asserted low. that is, the device may change from providing status information to valid data on dq7. even if the de vice has completed the prog ram or erase operation and dq7 has valid data, the data outputs on dq6-dq1 may be still invalid. valid data on dq7-d01 appears on successive read cycles. see the following for more information: table 6.27 , write operation status , shows the outputs for data# polling on dq7. table 6.5 , write operation status flowchart , shows the data# polling algorithm; and figure 10.15 , data# polling timings (during embedded algorithm) , shows the data# polling timing diagram. february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 47 data sheet (advance information) figure 6.5 write operation status flowchart dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address in the same bank, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and du ring the sector erase time-out. during an embedded program or erase algorithm operatio n, successive read cycles to any address cause dq6 to toggle. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sect ors selected for erasing are protected, dq6 toggles for approximately t asp [all sectors protected toggle time], then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprote cted sectors, and ignores the selected sectors that are protected. start read 1 dq7=valid data? yes no read 1 dq5=1? yes no write buffer programming? yes no device busy, re-poll read3 dq1=1? yes no read 2 read 3 read 2 read 3 read 2 read 3 read3 dq1=1 and dq7 ? valid data? yes no (note 4) write buffer operation failed dq6 toggling? yes no timeout (note 1) (note 3) programming operation? dq6 toggling? yes no yes no dq2 toggling? yes no erase operation complete device in erase/suspend mode program operation failed device error erase operation complete read3= valid data? yes no notes: 1) dq6 is toggling if read2 dq6 does not equal read3 dq6. 2) dq2 is toggling if read2 dq2 does not equal read3 dq2. 3) may be due to an attempt to program a 0 to 1. use the reset command to exit operation. 4) write buffer error if dq1 of last read =1. 5) invalid state, use reset command to exit operation. 6) valid data is the data that is intended to be programmed or all 1's for an erase operation. 7) data polling algorithm valid for all operations except advanced sector protection. 8) it can fail if one tries to program dq7 from '0' to '1' device busy, re-poll device busy, re-poll device busy, re-poll (note 1) (note 2) (note 6) (note 5) 48 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) the system can use dq6 and dq2 toget her to determine whether a sector is actively erasing or is erase- suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq 6 stops toggling. howe ver, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternativ ely, the system can use dq7 (see the subsection on dq7: data# polling). if a program address falls within a protec ted sector, dq6 toggles for approximately t psp after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. see the following for additional information: figure 6.5 , write operation status flowchart ; figure 10.16 , toggle bit timings (during embedded algorithm) , and ta b l e s 6.26 and 6.27 . toggle bit i on dq6 requires either oe # or ce# to be de-asserted and reasse rted to show the change in state dq2: toggle bit ii the toggle bit ii on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. but dq2 cannot distinguish whether the sector is actively erasing or is erase- suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bi ts are required for sector and mode information. refer to table 6.26 to compare outputs for dq2 and dq6. see the fo llowing for additional information: figure 6.5 , the dq6: toggle bit i section, and figures 10.15 ? 10.18 . reading toggle bits dq6/dq2 whenever the system initially begins reading toggle bit st atus, it must read dq7 ? dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system notes a nd stores the value of the toggle bit after the first read. af ter the second read, the system compares the new value of the toggle bit with the first. if the toggle bit is not toggli ng, the device has completed the program or erases operation. the system can read array data on dq7 ? dq0 on the followin g read cycle. however, if after th e initial two read cycles, the system determines that the toggle bit is still toggling, the syste m also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether th e toggle bit is toggling, since the toggle bit may have stopped toggling just as dq 5 went high. if the toggle bit is no longer toggling, the device has successfully completed th e program or erases operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may conti nue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. refer to figure 6.5 for more details. note: when verifying the status of a wr ite operation (embedded program/e rase) of a memory bank, dq6 and dq2 toggle between high and low states in a series of consecutive and contiguous status read cycles. in order for this toggling behavior to be properly observ ed, the consecutive status bit reads must not be interleaved with read accesses to other memory banks. if it is not possible to temporarily prevent reads to table 6.26 dq6 and dq2 indications if device is and the system reads then dq6 and dq2 programming, any address at the bank being programmed toggles, does not toggle. actively erasing, at an address within a sector selected for erasure, toggles, also toggles. at an address within sectors not selected for erasure, toggles, does not toggle. erase suspended, at an address within a sector selected for erasure, does not toggle, toggles. at an address within sectors not selected for erasure, returns array data, returns array data. the system can read from any sector not selected for erasure. programming in erase suspend any address at the bank being programmed toggles, is not applicable. february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 49 data sheet (advance information) other memory banks, then it is recommended to use the dq7 status bit as the alternative method of determining the active or inactive status of the write operation. dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a 1 , indicating that th e program or erase cycle was not successfully completed. the device may output a 1 on dq5 if the system tries to program a 1 to a location that was previously programmed to 0 . only an erase operation can change a 0 back to a 1 . under this condition, the device halts the operation, and when the ti ming limit has been exceeded, dq5 produces a 1 . under both these conditions, the system must write the reset comm and to return to the read mode (or to the erase- suspend-read mode if a bank was previously in the erase-suspend-program mode). dq3: sector erase timeout state indicator after writing a sector erase comm and sequence, the system may read dq 3 to determ ine whether or not erasure has begun. (the sector erase ti mer does not apply to the chip eras e command.) if additional sectors are selected for erasure, the entire time-out also ap plies after each additional sector erase command. when the time-out period is comp lete, dq3 switches from a 0 to a 1 . if the time between additional sector erase commands from the system can be assumed to be less than t sea , the system need not monitor dq3. see the sector erase command sequ ence, for more details. after the sector erase command is wr itten, the system should re ad the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is 1 , the embedded erase algorithm has begun; all further commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is 0 , the device accepts additional sector erase commands. to ensure the command has been accepted, the system softwa re should check the status of dq3 prior to and following each sub-sequent sector erase command. if dq 3 is high on the second status check, the last command might not have been accepted. table 6.27 shows the status of dq3 relative to the other status bits. dq1: write to buffer abort dq1 indicates whether a write to buffer operation wa s aborted. under these conditions dq1 produces a 1 . the system must issue the write to buffer abort rese t command sequence to return the device to reading array data. see write buffer program ming operation for more details. notes 1. dq5 switches to 1 when an embedded program or embedded erase operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. data are invalid for addresses in a program suspended sector. 4. dq1 indicates the write to buffer abort status during write buffer programming operations. 5. the data-bar polling algorithm should be used for write buffer programming operations. note that dq7# during write buffer programming indicates the data-bar for dq7 data for the last loaded write-buffer address location . table 6.27 write operation status status dq7 (2) dq6 dq5 (1) dq3 dq2 (2) dq1 (4) standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle n/a program suspend mode (3) reading within program suspended sector invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) reading within non-program suspended sector data data data data data data erase suspend mode erase-suspend- read erase suspended sector 1 no toggle 0 n/a toggle n/a non-erase suspended sector data data data data data data erase-suspend-program dq7# toggle 0 n/a n/a n/a write to buffer (5) busy state dq7# toggle 0 n/a n/a 0 exceeded timing limits dq7# toggle 1 n/a n/a 0 abort state dq7# toggle 0 n/a n/a 1 50 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) 6.6 simultaneous read/write the simultaneous read/write f eature allows the host system to read da ta from one bank of memory while programming or erasing another bank of memory. an er ase operation may also be suspended to read from or program another location within the same bank (except the sector being erased). figure 10.21 , back-to-back read/write cycle timings , shows how read and write cycles may be initiated for simultaneous operation with zero latency. refer to the dc characteristics table for read-while-program and read-while-erase current specification. 6.7 writing commands/command sequences when the device is in asynchronous read, only a synchronous write operations are allowed. during an asynchronous write operation, the syst em must drive ce# and we# to v il and oe# to v ih when providing an address, command, and data. addresses are latched on the rising edge of avd#, while data is latched on the rising edge of we#. an erase oper ation can erase one sector, multiple sectors, or the entire device. table 5.1 ? table 5.3 indicate the address space that each sector occ upies. the device address space is divided into sixteen banks: for ns512p, all 16 banks contain 64-k word sectors while for ns256p and ns128p, banks 0 through 14 contain only 64 kword sectors, bank 15 cont ains 16-kword boot sectors in addition to 64 kword sectors. a bank address is the set of address bits required to uniquely select a bank. similarly, a sector address is the address bits required to uniquely select a sector. i cc2 in the dc characteristics section represents the active current s pecification for the write mode. ac characteristics-synchronous and ac characteristics-asynchronous contain timing specification tables and timing diagrams for write operations. 6.8 handshaking the handshaking fe ature allows the host system to det ect when data is ready to be read by simply monitoring the rdy pin which is a dedicated output and is controlled by ce#. 6.9 hardware reset the reset# input provides a hardware method of re setting the device to reading array data. when reset# is driven low for at least a period of t rp , the device immediately terminates an y operation in progress, tristates all outputs, resets the configuration register, and ig nores all read/write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. to ensure data integrity the operation that was interrupted should be rein itiated once the device is ready to accept another command sequence. when reset# is held at v ss , the device draws cmos standby current (i cc4 ). if reset# is held at v il , but not at v ss , the standby current is greater. reset# may be tied to the system reset circuitry whic h enables the system to read the boot-up firmware from the flash memory upon a system reset. see figures 10.5 and 10.11 for timing diagrams. 6.10 software reset software reset is part of the command set (see table 11.1 ) that also returns the device to array read mode and must be used for the following conditions: 1. to exit autoselect mode 2. when dq5 goes high during write status operation that indicates program or erase cycle was not successfully completed 3. exit sector lock/unlock operation. 4. to return to erase-suspend-read mode if the device was previously in erase suspend mode. 5. after any aborted operations 6. exiting read configuration registration mode february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 51 data sheet (advance information) software functions and sample code note base = base address. the following is a c source code example of using the reset function. refer to the spansion low level driver user?s guide ( www.spansion.com ) for general information on spansion flash memory software development guidelines. /* example: reset (software reset of flash state machine) */ *( (uint16 *)base_addr + 0x000 ) = 0x00f0; the following are additional points to consider when using the reset command: ? this command resets the banks to t he read and address bits are ignored. ? reset commands are ignored once erasure has begun until the operation is complete. ? once programming begins, the device ignores reset commands until the operation is complete ? the reset command may be written between the cycles in a program command sequence before programming begins (prior to the thir d cycle). this resets the bank to which the system was writing to the read mode. ? if the program command sequence is written to a bank t hat is in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. ? the reset command may be also written during an autoselect command sequence. ? if a bank has entered the autoselect mode while in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. ? if dq1 goes high during a write buffer progra mming operation, the system must write the write to buffer abort reset command sequence to reset the device to reading array data. the standard reset command does not work during this condition. ? to exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset command sequence [see command table for details]. 6.11 programmable output slew rate control this feature allows the user to change the output slew rate during a read operation by setting the configuration register bit cr1.4. it allows 2 programmabl e slew rates. this feature is for users who do not want to run the part at its maximum speed and could live with a slower output sl ew rate thereby reducing noise variations at the output. table 6.28 reset (lld function = lld_resetcmd) cycle operation byte address word address data reset command write base + xxxh base + xxxh 00f0h table 6.29 programmable output slew rate mode description i ol & i oh 1 full drive (default) 100 a 2 half drive 50 a 52 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) 7. advanced sector protection/unprotection the advanced sector protec tion/unprotection feature disables or ena bles programming or erase operations in any or all sectors and can be implemented thr ough software and/or hardware methods, which are independent of each other. this sectio n describes the various methods of protecting data stored in the memory array. an overview of these methods in shown in figure 7.1 . figure 7.1 advanced sector protection/unprotection 7.1 lock register the lock register consists of 5 bits. the secured silicon sector protection bit is dq 0, persistent protection mode lock bit is dq1, password protection mode lock bi t is dq2, persistent sector protection otp bit is dq3 and volatile sector protection boot bit is dq4. if dq0 is 0 , it means that the cu stomer secured silicon area is locked and if dq0 is 1 , it means that it is unlocked. when dq2 is set to 1 and dq1 is set to 0 , the hardware methods software methods v pp = v il ( all sectors locked) wp# = v il (all boot sectors locked) password method (dq2) persistent method (dq1) lock register (one time programmable) ppb lock bit 1,2,3 64-bit password (one time protect) 1 = ppbs unlocked 0 = ppbs locked memory array sector 0 sector 1 sector 2 sector n-2 sector n-1 sector n 3 ppb 0 ppb 1 ppb 2 ppb n-2 ppb n-1 ppb n persistent protection bit (ppb) 4,5 dyb 0 dyb 1 dyb 2 dyb n-2 dyb n-1 dyb n dynamic protection bit (dyb) 6,7,8 6. 0 = sector protected, 1 = sector unprotected. 7. protect effective only if ppb lock bit is unlocked and corresponding ppb is 1 (unprotected). 8. volatile bits: defaults to protected after power up. 4. 0 = sector protected, 1 = sector unprotected. 5. ppbs programmed individually, but cleared collectively 1. bit is volatile, and defaults to 1 on reset. 2. programming to 0 locks all ppbs to their current state. 3. once programmed to 0 , requires hardware reset to unlock. 3. n = highest address sector. february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 53 data sheet (advance information) device can only be used in the persis tent protection mode. when the devic e is set to password protection mode, dq1 is required to be set to 1 and dq2 is required to be set to 0 . dq3 is programmed in the spansion factory. when the device is programmed to disable all ppb erase co mmand, dq3 outputs a 0 , when the lock register bits are read. si milarly, if the device is programmed to enable all ppb erase co mmand, dq3 outputs a 1 when the lock register bits are read. likewise the dq 4 bit is also programmed in the spansion factory. dq4 is the bit which indicates whether volatile sector protection bit (dyb) is protec ted or not after boot up. when the device is programmed to set all volatile se ctor protection bit protected after power up, dq4 outputs a 0 when the lock register bits are read. similarly, when the device is programmed to set all volatile sector protection bit unprotected after power up, dq4 outputs a 1 . each of these bits in the lock register are non-volatile. dq15 ? dq5 are reserved and are 1 s. for programming lock register bits refer to table 11.2 . notes 1. if the password mode is chosen, the password must be programmed and verified before setting the corresponding lock register bit. 2. it is recommended that a sector protection me thod to be chosen by programming dq1 or dq2 prior to shipment 3. after the lock register bits command set entry command sequence is written, reads and writes for bank 0 are disabled, while reads from ot her banks are allowed until exiting this mode. 4. if both lock bits are selected to be programmed (to zeros) at the same time, the operation aborts. 5. once the password mode lock bit is programmed, the persistent mode lock bit is permanently disabled, and no changes to the protection scheme are allowed. similarly, if the persistent mode lock bit is programmed, the password mode is permanently disabled. 6. during erase/program suspend, asp entry commands are not allowed. 7. data polling can be done immediately after the lock register programming command sequence (no delay required). note that status polling can be done only in bank 0. 8. reads from other banks (simultaneous operat ion) are not allowed during lock register programming. this restriction applies to both synchronous and asynchronous read operations. after selecting a sector protection method, each sect or can operate in any of the following three states: 1. constantly locked. the selected sectors are protecte d and can not be reprogrammed unless ppb lock bit is cleared via a password, hardware reset, or power cycle. 2. dynamically locked. the selected sectors are protect ed and can be altered via software commands. 3. unlocked. the sectors are unprotected and c an be erased and/or programmed. these states are controlled by the bit types described in sections 7.2 ? 7.6 . 7.2 persistent protection bits the persistent protection bits ar e unique and nonvolatile for each sector and have the same endurances as the flash memory. preprogramming and verification prio r to erasure are handled by the device, and therefore do not require system monitoring. lock register dq15-5 dq4 dq3 dq2 dq1 dq0 1 s dyb lock boot bit 0 = dyb bits power up protected (default) 1 = dyb bits power up unprotected ppb one time programmable bit 0 = all ppb erase command disabled 1 = all ppb erase command enabled password protection mode lock bit persistent protection mode lock bit secured silicon sector protection bit 54 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) notes 1. each ppb is individually programm ed and all are eras ed in parallel. 2. while programming ppb for a sector , array data can be read from any other bank, except bank 0 (used for data# polling) and the bank in which sector ppb is being programmed. 3. entry command disables reads and writes for the bank selected. 4. reads within that bank return the ppb status for that sector. 5. reads from other banks are allow ed while writes are not allowed. 6. all reads must be performed using the asynchronous mode. 7. the specific sector address (amax ? a14) are wr itten at the same time as the program command. 8. if the ppb lock bit is set, the ppb program or erase command does not execute and time out without programming or erasing the ppb. 9. there are no means for individually erasing a s pecific ppb and no specific sector address is required for this operation. 10. ppb exit command must be issued after the exec ution which resets the device to read mode and re-enables reads and writes for bank 0 11. the programming state of the ppb for a given sect or can be verified by writing a ppb status read command to the device as described by the flow chart shown in figure 7.2 . 12. during ppb program/erase data polling can be done synchronously. 13. if customers attempt to program or erase a prot ected sector, the device ignores the command and returns to read mode. february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 55 data sheet (advance information) figure 7.2 ppb program/erase algorithm 7.3 dynamic protection bits dynamic protection bits are volatile and unique for eac h sector and can be individually modified. dybs only control the protection scheme fo r unprotected sectors that have their ppbs cleared (erased to 1 ). by issuing the dyb set or clear command sequences, the dybs are set (programmed to 0 ) or cleared (erased to 1 ), thus placing each sector in the prot ected or unprotected state respective ly. this feature allows software to easily protect sectors against inadvertent changes ye t does not prevent the easy removal of protection when changes are needed. read byte twice addr = sa0 enter ppb command set. addr = ba program ppb bit. addr = sa dq5 = 1? yes yes yes no no no yes dq6 = toggle? dq6 = toggle? read byte. addr = sa pass fail exit ppb command set dq0 = '1' (erase) '0' (pgm.)? read byte twice addr = sa0 no wait 500 s 56 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) notes 1. the dybs can be set (programmed to 0 ) or cleared (erased to 1 ) as often as needed. 2. when the parts are first shipped, the dybs are set and programmed to 0 upon power up or reset. 3. the default state of dyb is protected after powe r up and all sectors can be modified depending on the status of ppb bit for that sector, (erased to 1 ). then the sectors can be modified depending upon the ppb state of that sector (see table 7.1 ). 4. it is possible to have sectors that are persistently locked with sectors that are left in the dynamic state. 5. the dyb set or clear commands for the dynamic se ctors signify protected or unprotectedstate of the sectors respectively. however, if there is a ne ed to change the status of the persistently locked sectors, a few more steps are required. first, the ppb lock bit must be cleared by either putting the device through a power cycle, or hardware reset. the ppbs can then be changed to reflect the desired settings. setting the ppb lock bit onc e again locks the ppbs, a nd the device operates normally again. 6. to achieve the best prot ection, it is recommended to execute the ppb lock bit set command early in the boot code and protect the boot code by holding wp# = v il . 7. data polling is not available for dyb program/erase. 8. dyb read data can be done synchronously. 9. if customers attempt to program or erase a prot ected sector, the device ignores the command and returns to read mode. 7.4 persistent protection bit lock bit the persistent protection bit lock bit is a global vo latile bit for all sectors. when set (programmed to 0 ), it locks all ppbs and when cleared (programmed to 1 ), allows the ppbs to be ch anged. there is only one ppb lock bit per device. notes 1. if the password mode is chosen, then the passw ord must be programmed and verified before setting the corresponding lock register bit. 2. no software command sequence unlocks this bit unless the device is in the password protection mode; only a hardware reset or a power up clears this bit. 3. the ppb lock bit must be set (programmed to 0 ) only after all ppbs are c onfigured to the desired settings. 7.5 password protection method the password protection method allows an even higher leve l of security than the pers istent sector protection mode by requiring a 64 bit password for unlocking the device ppb lock bit. in addition to this password requirement, after power up and reset, the ppb lock bit is set 0 to maintain the password mode of operation. successful execution of the password unlock command by entering the entire password clears the ppb lock bit, allowing for sector ppbs modifications. notes 1. there is no special addressing order required for programming the password. once the password is written and verified, the password mode locking bit must be set in order to prevent access. 2. the password program command is only capable of programming 0 s. programming a 1 after a cell is programmed as a 0 results in a time out with the cell as a 0 . 3. the password is all 1 s when shipped from the factory. 4. all 64-bit password combinations are valid as a password. 5. there is no means to verify what the password is after it is set. 6. the password mode lock bit, once set, prevents reading the 64-bit password on the data bus and further password programming. february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 57 data sheet (advance information) 7. the password mode lock bit is not erasable. 8. the lower two address bits (a1 ? a0) are valid during the password read, password program, and password unlock. 9. the exact password must be entered in order for the unlocking function to occur. 10. the password unlock command cannot be issued any faster than 1 s at a time to prevent a hacker from running through all the 64-bit combin ations in an attempt to correctly match a password. 11. approximately 1 s is required for unlocking the devi ce after the valid 64-bit password is given to the device. 12. password verification is only allowed during the password programming operation. 13. all further commands to the password region are disabled and all operations are ignored. 14. if the password is lost after setting the password mode lock bit, there is no way to clear the ppb lock bit. 15. entry command sequence must be issued prior to any of any operation and it disables reads and writes for bank 0. reads and writes for other banks excluding bank 0 are allowed. 16. if the user attempts to program or erase a pr otected sector, the device ignores the command and returns to read mode. 17. a program or erase command to a protected sector enables status polling and returns to read mode without having modified the c ontents of the protected sector. 18. the programming of the dyb, ppb, and ppb lock for a given sector can be verified by writing individual status read commands dyb status, ppb status, and ppb lock status to the device. 58 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) figure 7.3 lock register program algorithm 7.6 advanced sector protection software examples write unlock cycles: address 555h, data aah address 2aah, data 55h write enter lock register command: address 555h, data 40h program lock register data address xxxh, data a0h address 77h*, data pd unlock cycle 1 unlock cycle 2 xxxh = address don?t care * not on future devices program data (pd): see text for lock register definitions caution: lock register can only be progammed once. wait 4 s (recommended) pass. write lock register exit command: address xxxh, data 90h address xxxh, data 00h device returns to reading array. perform polling algorithm (see write operation status flowchart) yes yes no no done? dq5 = 1? error condition (exceeded timing limits) fail. write rest command to return to reading array. table 7.1 sector protection schemes unique device ppb lock bit 0 = locked 1 = unlocked sector ppb 0 = protected 1 = unprotected sector dyb 0 = protected 1 = unprotected sector protection status any sector 0 0 x protected through ppb any sector 0 0 x protected through ppb any sector 0 1 1 unprotected any sector 0 1 0 protected through dyb any sector 1 0 x protected through ppb any sector 1 0 x protected through ppb any sector 1 1 0 protected through dyb any sector 1 1 1 unprotected february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 59 data sheet (advance information) table 7.1 contains all possibl e combinations of the dyb, ppb, and ppb lock bit relating to the status of the sector. 7.7 hardware data protection methods the device offers two main types of data protec tion at the sector level via hardware control: ? when wp# is at v il , the highest two sectors are locked (device specific). ? when v pp is at v il , all sectors are locked. there are additional methods by which intended or acci dental erasure of any se ctors can be prevented via hardware means. the following subs ections describes these methods: wp# method the write protect feature provides a hardware method of protecting the highest two sectors (ns256p and ns128p). this function is provided by the wp# pin and overrides the pr eviously discussed sector protection/ unprotection method. if the system asserts v il on the wp# pin, the device disables progr am and erase functions in the highest two sectors (ns256p and ns128p) as well as secured silicon area. if the system asserts v ih on the wp# pin, the device reverts to whet her the boot sectors we re last set to be protected or unprotected. that is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected. note that the wp# pin must not be left floating or un connected as inconsistent behavior of the device may result. the wp# pin must be held stable during a command sequence execution v pp method this method is similar to above, e xcept it protects all sectors (inclu ding the secured silicon area). once v pp input is set to v il , all program and erase functions are disa bled and hence all sectors are protected. low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this protects data during v cc power up and power down. the command register and all internal program/erase ci rcuits are disabled, and the device resets to reading array data. subsequent wr ites are ignored until v cc is greater than v lko . the system must provide the proper signals to the control inputs to prevent unintentional writes when v cc is greater than v lko . write pulse glitch protection noise pulses of less than 3 ns (typical) on oe#, ce# or we # do not initiate a write cycle. power-up write inhibit if we# = ce# = reset# = v il and oe# = v ih during power up, the device d oes not accept commands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power up. 60 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) 8. power conservation modes 8.1 standby mode when the system is not reading or writing to the device , it can place the device in the standby mode. in this mode, current consumption is greatl y reduced, and the outputs are plac ed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# and reset# inputs are both held at v cc 0.2 v. the device requires standard access time (t ce ) for read access, before it is ready to read data. if the device is deselected during erasure or programming, the device draws active current until the operation is completed. i cc3 in the dc characteristics section represents the standby current specification 8.2 automatic sleep mode the automatic sleep mode minimizes flash device e nergy consumption while in asynchronous mode. the device automatically enables this mode when addresses remain stable for t acc + 20 ns. the automatic sleep mode is independent of the ce#, we#, and oe# contro l signals. standard address access timings provide new data when addresses are changed. while in sleep mo de, output data is latched and always available to the system. while in synchronous mode, the automati c sleep mode is disabled. note that a new burst operation is required to provide new data. i cc6 in the dc characteristics section represen ts the automatic sleep mode current specification. 8.3 hardware reset# input operation the reset# input provides a hardware method of re setting the device to reading array data. when reset# is driven low for at least a period of t rp , the device immediately terminates an y operation in progress, tristates all outputs, resets the configuration register, and ig nores all read/write commands for the duration of the reset# pulse. the device also resets the internal state ma chine to reading array data. the ope ration that was interrupted should be reinitiated once the device is ready to accept another command sequence to ensure data integrity. when reset# is held at v ss 0.2 v, the device draw s cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.2 v, the standby current is greater. reset# may be tied to the system reset circuitry and th us, a system reset also resets the flash memory, enabling the system to read the boot -up firmware from the flash memory. 8.4 output disable (oe#) when the oe# input is at v ih , output from the device is disabled. the outputs are placed in the high impedance state. february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 61 data sheet (advance information) 9. secured silicon sector flash memory region the secured silicon sector provides an extra flash memo ry region that enables permanent part identification through an electronic serial number (esn). the secured silicon sector is 256 word s in length that consists of 128 words for factory data and 128 words for custome r-secured areas. all secured silicon reads outside of the 256-word address range returns invalid data. the fact ory indicator bit, dq7, (a t autoselect address 03h) is used to indicate whether or not the factory secured silicon sector is locked when shipped from the factory. the customer indicator bit (dq6) is used to indicate whether or not the customer secured silicon sector is locked when shipped from the factory. please note the following general conditions: ? while secured silicon sector access is enabled, simultaneous operations are allowed except for bank 0. ? on power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. ? reads can be performed in the asynchronous or synchronous mode. ? burst mode reads within secured silicon sector wrap from address ffh back to address 00h. ? reads outside of sector 0 return memory array data. ? continuous burst read past the maximum address is undefined. ? sector 0 is remapped from memory array to secured silicon sector array. ? once the secured silicon sector entry command is issued, the secured silicon sector exit command must be issued to exit secured silicon sector mode. ? the secured silicon sector is not accessible when the device is executing an embedded program or embedded erase algorithm. 9.1 factory secured silicon sector the factory secured silicon sector is always protected when shipped fr om the factory and has the factory indicator bit (dq7) permanently set to a 1 . this prevents cloning of a fa ctory locked part and ensures the security of the esn and customer code once the product is shipped to the field. these devices are available pre pr ogrammed with one of the following: ? a random, 8 word secure esn only within the factory secured silicon sector ? customer code within the customer secured silicon sector through the spansion tm programming service. ? both a random, secure esn and customer code through the spansion programming service. customers may opt to have their code programmed th rough the spansion programming services. spansion programs the customer's code, with or without t he random esn. the devices are then shipped from the spansion factory with the factory secured silicon sector and customer secured s ilicon sector permanently locked. contact your local representative for details on using spansion programming services. 9.2 customer secured silicon sector the customer secured silicon sector is typically shipped unprotected (dq6 set to 0 ), allowing customers to utilize that sector in any manner they choose. if the security feature is not required, the customer secured silicon sector can be treated as an additional flash memory space. please note the following: ? once the customer secured silicon sector area is pr otected, the customer indicator bit is permanently set to 1 . table 9.1 secured silicon sector secure sector addresses sector sector size address range customer 128 words 000080h-0000ffh factory 128 words 000000h-00007fh 62 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) ? the customer secured silicon sector can be read any number of times, but can be programmed and locked only once. the customer secured silicon sector lock must be used with caution as once locked, there is no procedure available for unlocking the cust omer secured silicon sector area and none of the bits in the customer secured silicon sect or memory space can be modified in any way. ? the accelerated programming (v pp ) and unlock bypass functions are not available when programming the customer secured silicon sector, but reading in banks 1 through 15 is available. ? once the customer secured silicon sector is locked and verified, the system must write the exit secured silicon sector region command sequence which return the device to the memory array at sector 0. 9.3 secured silicon sector en try and exit command sequences the system can access the secured s ilicon sector region by issuing th e three-cycle enter secured silicon sector command sequence. the device continues to access the secured silicon sector region until the system issues the four-cycle exit secu red silicon sector command sequence. see command definition table [secured silicon sector command table, appendix table 11.1 for address and data requirements for both command sequences. the secured silicon sector entry command allows the following commands to be executed ? read customer and factor y secured silicon areas ? program the customer secured silicon sector after the system has written the enter secured silicon sector command sequence, it may read the secured silicon sector by using the addresses normally occupied by sector sa0 within the memory array. this mode of operation continues unt il the system issues the exit secured silicon sector command sequence, or until power is removed from the device. software functions and sample code the following are c functions and source code examples of using the secured silicon sector entry, program, and exit commands. refer to the spansion low level driver user?s guide ( www.spansion.com ) for general information on spansion flash memory software development guidelines. note base = base address. /* example: secured silicon sector entry command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0088; /* write secured silicon sector entry cmd */ note base = base address. table 9.2 secured silicon sector entry (lld function = lld_secsisectorentrycmd) cycle operation byte address word address data unlock cycle 1 write base + aaah base + 555h 00aah unlock cycle 2 write base + 554h base + 2aah 0055h entry cycle write base + aaah base + 555h 0088h table 9.3 secured silicon sector program (lld function = lld_programcmd) cycle operation byte address word address data unlock cycle 1 write base + aaah base + 555h 00aah unlock cycle 2 write base + 554h base + 2aah 0055h program setup write base + aaah base + 555h 00a0h program write word address word address data word february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 63 data sheet (advance information) /* once in the secured silicon sector mode, you program */ /* words using the programming algorithm. */ note base = base address. /* example: secured silicon sector exit command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0090; /* write secured silicon sector exit cycle 3 */ *( (uint16 *)base_addr + 0x000 ) = 0x0000; /* write secured silicon sector exit cycle 4 */ table 9.4 secured silicon sector exit (lld function = lld_secsisectorexitcmd) cycle operation byte address word address data unlock cycle 1 write base + aaah base + 555h 00aah unlock cycle 2 write base + 554h base + 2aah 0055h exit cycle 3 write base + aaah base + 555h 0090h exit cycle 4 write any address any address 0000h 64 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) 10. electrical specifications 10.1 absolute maximum ratings notes 1. minimum dc voltage on input or i/os is ?0.5 v. during voltage transitions, inputs or i/os may undershoot v ss to ?2.0 v for periods of up to 20 ns. see figure 10.1 . maximum dc voltage on input or i/os is v cc + 0.5 v. during voltage transitions outputs may overshoot to v cc + 2.0 v for periods up to 20 ns. see figure 10.2 . 2. minimum dc input voltage on pin v pp is ?0.5v. during voltage transitions, v pp may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 10.1 . maximum dc voltage on pin v pp is +9.5 v, which may overshoot to 10.5 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one seco nd. 4. stresses above those listed under absolute maximum ratings may cause permanent damage to the de vice. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this d ata sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. figure 10.1 maximum negative overshoot waveform figure 10.2 maximum positive overshoot waveform 10.2 operating ranges note operating ranges define those limits between wh ich the functionality of the device is guaranteed. storage temperature plastic packages ?65c to +150c ambient temperature with power applied ?65c to +125c voltage with respect to ground: all inputs and i/os except as noted below (1) ?0.5 v to + 2.5 v v cc (1) ?0.5 v to +2.5 v v pp (2) ?0.5 v to +9.5 v output short circuit current (3) 100 ma 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 1.0 v wireless (i) devices ambient temperature (t a ) ?25c to +85c supply voltages v cc supply voltages +1.70 v to +1.95 v february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 65 data sheet (advance information) 10.3 dc characteristics 10.3.1 cmos compatible notes 1. maximum i cc specifications are tested with v cc = v cc max. 2. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 3. i cc active while embedded erase or embedded program is in progress. 4. device enters automatic sleep mode when addresses are stable for t acc + 20 ns. typical sleep mode current is equal to i cc3 . 5. total current during accelerated programming is the sum of v pp and v cc currents. 6. v ccq = v cc during all icc measurements. 7. clock frequency 66 mhz and in continuous mode. 8. for i cc6 , when v ih = v io , v il = v ss . table 10.1 dc characteristi cs?cmos compatible parameter description test conditions (1) min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1 a i ccb v cc active burst read current ce# = v il , oe# = v ih , we# = v ih , burst length = 8 108 mhz 33 44 ma 83 mhz 26 36 ma 66 mhz 24 33 ma ce# = v il , oe# = v ih , we# = v ih , burst length = 16 108 mhz 30 40 ma 83 mhz 26 38 ma 66 mhz 24 35 ma ce# = v il , oe# = v ih , we# = v ih , burst length = 32 108 mhz 25 33 ma 83 mhz 28 40 ma 66 mhz 26 37 ma ce# = v il , oe# = v ih , we# = v ih , burst length = continuous 108 mhz 32 44 ma 83 mhz 30 42 ma 66 mhz 28 39 ma i cc1 v cc active asynchronous read current (2) ce# = v il , oe# = v ih , we# = v ih 10 mhz 40 80 ma 5 mhz 20 40 ma 1 mhz 10 20 ma i cc2 v cc active write current (3) ce# = v il , oe# = v ih , v pp = vi h v pp 15a v cc <20 <40 ma i cc3 v cc standby current (4) ce# = reset# = v cc 0.2 v v pp 15a v cc 20 70 a i cc4 v cc reset current reset# = v il, clk = v il 150 250 a i cc5 v cc active current (read while write) ce# = v il , oe# = v ih , v pp = v ih , (7) 50 60 ma i cc6 v cc sleep current ce# = v il , oe# = v ih 540a i ppw accelerated program current (5) ce# = v il , oe# = v ih, v pp = 9.5 v v pp <7 <10 ma v cc <15 <20 ma v il input low voltage ?0.2 0.4 v v ih input high voltage v cc ? 0.4 v cc + 0.4 v ol output low voltage i ol = 100 a, v cc = v cc min = v cc 0.1 v v oh output high voltage i oh = ?100 a, v cc = v cc min v cc ? 0.1 v v hh voltage for accelerated program 8.5 9.5 v v lko low v cc lock-out voltage 1.4 v 66 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) 10.4 test conditions figure 10.3 test setup 10.5 key to switching waveforms 10.6 switching waveforms figure 10.4 input waveforms and measurement levels note v cc and v ccq must be ramped simultaneously for proper power-up. table 10.2 test specifications test condition all speed options unit output load capacitance, c l, (including jig capacitance) 30 pf input rise and fall times 1.0 ? 1.50 ns input pulse levels 0.0 ? v cc v input timing measurement reference levels v cc /2 v output timing measurement reference levels v ccq /2 v c l device under te s t waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) table 10.3 v cc power-up with no ramp rate restriction parameter description test setup time unit t vcs v cc setup time min 30 s t rh time between reset# (high) and ce# (low) min 200 ns v cc 0.0 v output measurement level input v cc /2 v ccq /2 all inputs and outputs february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 67 data sheet (advance information) figure 10.5 v cc power-up diagram 10.7 clk characterization figure 10.6 clk characterization 10.8 ac characteristics 10.8.1 synchronous/burst read v cc reset# t vcs t rh ce# v cc min v ih table 10.4 clk characterization parameter description 66 mhz 83 mhz 108 mhz unit f clk clk frequency max 66 83 108 mhz min 60 khz in 8 word burst, 120 khz in 16 word burst, 250 khz in 32 word burst, 1 mhz in continuous mode t clk clk period min 15.1 12.5 9.26 ns t cl /t ch clk low/high time min 0.40 t clk ns max 0.60 t clk t cr clk rise time max 3.0 2.5 1.5 ns t cf clk fall time t clk t cl t ch t cr t cf clk table 10.5 synchronous/burst read parameter description 66 mhz 83 mhz 108 mhz unit jedec standard t iacc synchronous access time max 80 ns t bacc burst access time valid clock to output delay max 11.2 9 7.6 ns t acs address setup time to clk (1) min 4 ns t ach address hold time from clk (1) min655ns t bdh data hold time min 3 3 2 ns t rdy chip enable to rdy active max 10 ns 68 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) notes 1. addresses are latched on the rising edge of clk 2. synchronous access time is calculated using the formula (#of ws ? 1)*(clock period) + (t bacc or clock to out) 3. not 100% tested for t cez , t oez . figure 10.7 8-word linear synchronous single data rate burst with wrap around notes 1. figure shows for illustration the total nu mber of wait states set to seven cycles. 2. the device is configured synchronous single data rate mode and rdy active with data. 3. ce# (high) drives the rdy to hi-z while oe# (high) drives the a/dq15 ? a/dq0 pins to hi-z t oe output enable to rdy low max 9 9 9 ns t cez chip enable to high z max 10 10 10 ns t oez output enable to high z max 10 10 10 ns t ces ce# setup time to clk min 4 ns t racc ready access time from clk max 11.2 9 7.5 ns t cas ce# setup time to avd# min 0 ns t avds avd# low to clk setup time min 5 ns t avdh avd# hold time to clk min 3 ns t avd0 avd# high to oe# low min 0 ns t avd avd# pulse min 6 ns table 10.6 synchronous wait state requirements max frequency wait state requirement frequency 14 mhz 2 14 < frequency 27mhz 3 27 mhz < frequency 40 mhz 4 40 mhz < frequency 54 mhz 5 54 mhz < frequency 66 mhz 6 66 mhz < frequency 80 mhz 7 80 mhz < frequency 95 mhz 8 95 mhz < frequency 108 mhz 9 table 10.5 synchronous/burst read parameter description 66 mhz 83 mhz 108 mhz unit jedec standard dc dd oe# a/dq15 ? a/dq0 amax ? a16 ac avd# rdy clk ce# t ces t acs t avds t avd t ach t oe t bdh de db 7 cycles for initial access is shown as an illustration. hi-z t racc 1234567 t bacc t rdy t iacc ac february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 69 data sheet (advance information) figure 10.8 8-word linear single data read synchronous burst without wrap around notes 1. figure shows for illustration the total nu mber of wait states set to seven cycles. 2. the device is configured synchronous single data rate mode and rdy active with data. 3. ce# (high) drives the rdy to hi-z while oe# (high) drives the a/dq15 ? a/dq0 pins to hi-z 10.8.2 asynchronous mode read dc dd oe# a/dq15? a/dq0 amax? a16 ac avd# rdy clk ce# t ces t acs t avds t avd t ach t oe t iacc t bdh de df d13 7 cycles for initial access shown. hi-z t racc 1234567 t rdys t bacc t cr d10 t racc ac table 10.7 asynchronous mode read parameter description 66 mhz 83 mhz 108 mhz unit jedec standard t ce access time from ce# low typ 83 ns t acc asynchronous access time max 80 ns t avdp avd# low time min 7.5 ns t aavds address setup time to rising edge of avd# min 5 ns t aavdh address hold time from rising edge of avd# min 3.5 ns t oe output enable to output valid max 9 9 9 ns t oeh output enable hold time read min 0 ns toggle and data# polling min 10 10 10 ns t oez output enable to high z max 10 10 10 ns t cas ce# setup time to avd# min 0 ns 70 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) figure 10.9 asynchronous mode read with latched addresses note ra = read address, rd = read data. figure 10.10 asynchronous mode read note ra = read address, rd = read data. 10.8.3 hardware reset (reset#) t ce we ce# oe# valid rd t acc t oeh t oez t aavdh =0ns t avdp t aavds avd# ra t cas amax? a16 a/dq15? a/dq0 ra t oe t ce we# amax ? a16 ce# oe# valid rd t acc t oeh t oe a/dq15 ? a/dq0 t oez t aavdh t avdp t aavds avd# ra ra table 10.8 warm reset parameter description all speed options unit jedec std t rp reset# pulse width min 50 ns t rh reset high time before read min 200 ns t rph reset# low to ce# low min 10 s february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 71 data sheet (advance information) figure 10.11 reset timings 10.8.4 erase/program timing notes 1. not 100% tested. 2. in asynchronous operation timing, addresses are latched on the rising edge of avd#. 3. see the erase and programming performance section for more information. does not include the preprogramming time. reset# t rph t rp ce#, oe# t rh table 10.9 erase/program timing parameter description 66 mhz 83 mhz 108 mhz unit jedec standard t avav t wc write cycle time (1) min 60 ns t avwl t as address setup time (2) synchronous min 4ns asynchronous 4 ns t wlax t ah address hold time (2) synchronous min 3.5 asynchronous 3.5 t avdp avd# low time min 6 ns t dvwh t ds data setup time min 20 ns t whdx t dh data hold time min 0 ns t ghwl t ghwl read recovery time before write min 0 ns t cas ce# setup time to avd# min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 25 ns t whwl t wph write pulse width high min 20 ns t sr/w latency between read and write operations min 0 ns t vid v pp rise and fall time min 500 ns t vids v pp setup time (during accelerated programming) min 1 s t elwl t cs ce# setup time to we# min 4 ns t avsw avd# setup time to we# min 6 ns t avhw avd# hold time to we# min 4 ns t sea sector erase accept time out min 50 s t esl erase suspend latency min 20 s t psl program suspend latency min 20 s t asp toggle time during erase within a protected sector typ 280 s t psp toggle time during programming within a protected sector typ 1 s t ers erase resume to erase suspend min 30 s t prs program resume to program suspend min 30 s 72 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) figure 10.12 asynchronous program operation timings notes 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. in progress and complete refer to status of program operation. 3. clk can be either v il or v ih . figure 10.13 chip/sector erase command sequence note sa is the sector address for sector erase. oe# ce# avd we clk v cc t as t w t ah t wc t wph pa t vcs t cs t d t ch in progress va complete va program command sequence (last two cycles) read status data t ds v ih v il t avdp a0h 555h pd t cas a/dq15? a/dq0 amax? a16 va va pa 555h t avsw t avhw oe# ce# avd we clk v cc t as t ah t wc sa t vcs t cs t ch in progress t whwh2 va complete va erase command sequence (last two cycles) read status data t ds 10h for chip erase 555h for chip erase v ih v il t avdp 55h 2aah 30h 2aah sa va va t dh t wph t wp a/dq15? a/dq0 amax? a16 february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 73 data sheet (advance information) figure 10.14 accelerated unlock bypass programming timing note use setup and hold times from conventional program operation. figure 10.15 data# polling timings (during embedded algorithm) notes 1. status reads in figure are shown as asynchronous. 2. va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete, and data# polling outputs true data. figure 10.16 toggle bit timings (during embedded algorithm) notes 1. status reads in figure are shown as asynchronous. 2. va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete, the toggle bits stop toggling. ce# avd# we# oe# v pp don't care don't care a0h pa pa pd v hh 1 s v il or v ih t vids a/dq15? a/dq0 amax? a16 we# ce# oe high z t oe high z avd# t oeh t ce t ch t oez status data status data t acc va va va va a/dq15? a/dq0 amax? a16 t cez we# ce# oe high z t oe high z avd# t oeh t ce t ch t oez t cez t acc va va a/dq15? a/dq0 amax? a16 status data status data va va 74 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) figure 10.17 synchronous data polling timings/toggle bit timings notes 1. the timings are similar to synchronous read timings. 2. va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete, the toggle bits stop toggling. 3. rdy is active with data (d8 = 0 in the configuration register). when d8 = 1 in the configuration register, rdy is active one clock cycle before data. figure 10.18 dq2 vs. dq6 note dq2 toggles only when read at an address within an erase-suspended se ctor. the system may use oe# or ce# to toggle dq2 and dq6. figure 10.19 latency with boundary crossing notes 1. rdy active with data (cr0.8 = 0 in the configuration register). 2. rdy active one clock cycle before data (cr0.8 = 1 in the configuration register). 3. figure shows the device not crossing a bank in the process of performing an erase or program. ce# clk avd# oe# rdy status data status data va va t iacc t iacc a/dq15? a/dq0 amax? a16 va va enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complet e erase suspend suspend program resume embedded erasing clk address (hex) d124 d125 d126 d127 d128 d129 d130 (stays high) avd# rdy (note 1) data oe#, ce# (stays low) address boundary occurs every 128 words, beginning at address 00007fh: (0000ffh, 00017fh, etc.) address 000000h is also a boundary crossing. 7c 7d 7e 7f 7f 80 81 82 83 latency rdy (note 2) latency t racc t racc t racc t racc invalid february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 75 data sheet (advance information) figure 10.20 wait state configuration register setup note the addresses are latched by rising edge of clk. table 10.10 example of programmable wait states cr1.0 programmable wait state (see note) 0000 = initial data is valid on the 2nd rising clk edge after addresses are latched cr0.13 0001 3rd cr0.12 0010 4th cr0.11 0011 5th 0100 6th 0101 7th 0110 = reserved 0111 1000 = initial data is valid on the 8th rising clk edge after addresses are latched 1001 9th ? 1101 = initial data is valid on the 13th rising clk edge avd# transition to v ih (default) ? 1110 1111 = reserved data avd# oe# clk 1 2345 d0 d1 0 6 1 7 3 total number of clock cycles following addresses being latched rising edge of next clock cycle following last wait state triggers next burst data total number of clock edges following addresses being latched 24 6 57 76 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) figure 10.21 back-to-back read/write cycle timings note breakpoints in waveforms indicate that system may alternately read array data from the non-busy bank while chec king the status of the program or erase operation in the busy bank. the system should read status twice to ensure valid information. oe# ce# we# t oeh a/dq15? a/dq0 avd# pd/30h aah ra pa/sa t wc t ds t dh t rc t rc t oe t as t ah t acc t oeh t wp t ghwl t oez t wc t sr/w last cycle in program or sector erase command sequence read status (at least two cycles) in same bank and/or array data from other bank begin another write or program command sequence rd ra 555h rd amax? a16 pa/sa t wp ra ra 555h february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 77 data sheet (advance information) 10.9 erase and programming performance notes 1. typical program and erase times assume the following conditions: 25 c, 1.8 v v cc , 10,000 cycles using checkerboard patterns. 2. under worst case conditions of 90c, v cc = 1.70 v, 100,000 cycles. 3. in the pre-programming step of the embedded erase algorithm, all words are programmed to 00h before erasure. 4. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 11.1, memory array commands on page 78 and table 11.2, sector protection commands on page 80 for further information on command definitions. table 10.11 erase and programming performance parameter typ (1) max (2) unit comments sector erase time 64 kword v cc 0.8 3.5 s excludes 00h programming prior to erasure (3) 16 kword v cc 0.15 2.0 64 kword v pp 0.8 3.5 16 kword v pp 0.15 2.0 sector erase time 64 kword v cc 0.90 5.00 includes 00h programming prior to erasure (3) 16 kword v cc 0.45 1.85 64 kword v pp 0.70 3.75 16 kword v pp 0.35 1.40 chip erase time v cc 77 (ns128p) 154 (ns256p) 306 (ns512p) 154 (ns128p) 308 (ns256p) 612 (ns512p) s word programming time v cc 40 400 s excludes system level overhead (4) v pp 24 240 effective word programming time utilizing program write buffer v cc 9.4 94 s v pp 660 total 32-word buffer programming time v cc 300 3000 v pp 192 1920 chip programming time (using 32 word buffer) v cc 78.6 (ns128p) 157.3 (ns256p) 314.6 (ns512p) 157.3 (ns128p) 314.6 (ns256p) 629.2 (ns512p) s excludes system level overhead (4) v pp 51 (ns128p) 101 (ns256p) 202 (ns512p) 102 (ns128p) 202 (ns256p) 404 (ns512p) erase suspend/erase resume min 20 s program suspend/program resume min 20 s 78 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) 11. appendix this section contains information relating to softwar e control or interfacing with the flash device. for additional information and assistance regarding software, see www.spansion.com . legend x = don?t care. ra = read address. rd = read data. pa = program address. addresses latch on the rising edge of th e avd# pulse or active edge of clk, whichever occurs first. pd = program data. data latches on the rising edg e of we# or ce# pulse, whichever occurs first. sa = sector address. ns128p = a22 ? a14; ns256p = a23 ? a14. table 11.1 memory array commands command sequence (notes) cycles bus cycles ( 1 , 2 , 3 , 4 , 5 , 6 ) first second third fourth fifth sixth addr data (19) addr data (19) addr data (19) addr data (19) addr data (19) addr data (19) asynchronous read (7) 1ra rd reset (8) 1 xxx f0 autoselect (9) manufacturer id 4 555 aa 2aa 55 (ba) 555 90 (ba) x00 0001 device id (10) 6 555 aa 2aa 55 (ba) 555 90 (ba) x01 3x7e (ba)x 0e (10) (ba) x0f (10) indicator bits 4 555 aa 2aa 55 (ba) 555 90 (ba) x07 (12) sector unlock/lock verify (11) 4 555 aa 2aa 55 (sa) 555 90 (sa) x02 0000/ 0001 revision id 4 555 aa 2aa 55 (ba) 555 90 (ba) x03 single word program 4 555 aa 2aa 55 555 a0 pa data write to buffer (17) 6 555 aa 2aa 55 sa 25 sa wc pa pd wbl pd write buffer to flash 1 sa 29 write to buffer abort reset (10) 3 555 aa 2aa 55 555 f0 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 program/erase suspend (15) 1ba b0 program/erase resume (16) 1ba 30 set configuration register ( 21 , 22 , 24 ) 5 555 aa 2aa 55 555 d0 x00 cr0 x01 cr1 read configuration register 4 555 aa 2aa 55 555 c6 x0 (0 or 1) cr (0 or 1) cfi query (17) 1 (ba) 55 98 unlock bypass mode (23) unlock bypass entry (18) 3 555 aa 2aa 55 555 20 unlock bypass program (13) , (14) 2xx a0 pa pd unlock bypass sector erase (13) , (14) 2xx80sa30 unlock bypass erase (13) , (14) 2xx 80 xxx 10 unlock bypass cfi (13) , (14) 1xx 98 unlock bypass reset 2 xx 90 xxx 00 february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 79 data sheet (advance information) ba = bank address. ns128p = a22 ? a20, and a19; ns064p = a21, a20 ? a18; ns256p = a23 ? a20.cr = configuration register data bits d15 ? d0. wbl = write buffer location. address must be within the same write buffer page as pa. wc = word count. number of write buffer locations to load minus 1. notes 1. see table 6.1 for description of bus operations. 2. all values are in hexadecimal. 3. except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the autoselect commands, fourth cycle of the configuration register verify and password verify commands, and any cycle reading at rd(0) and rd(1). 4. data bits dq15 ? dq8 are don?t care in command sequences, except for rd, pd, wd, pwd, and pwd3 ? pwd0. 5. unless otherwise noted, address bits amax ? a14 are don?t cares. 6. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. the system must write the reset command to return the device to reading array data. 7. no unlock or command cycles required when bank is reading array data. 8. the reset command is required to return to reading array data (o r to the erase-suspend-read mode if previously in erase suspe nd) when a bank is in the autoselect mode, or if dq5 goes high (while the bank is providing status information) or performing sector loc k/unlock. 9. the fourth cycle of the autoselect address is a read cycle. the system must provide the bank address. 10. (ba) + 0eh ----> for ns128 = 43h, ns256 = 41h, ns512 = 3fh (ba) + 0fh ----> for ns128/256/512 = 00h 11. the data is 0000h for an unlocked sector and 0001h for a locked sector 12. see table 6.12, autoselect addresses on page 34 . 13. the unlock bypass command sequence is required prior to this command sequence. 14. the unlock bypass reset command is required to return to reading array data when the bank is in the unlock bypass mode. 15. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the program/erase suspend command is valid only during a program/ erase operation, and requires the bank address. 16. the program/erase resume command is valid only during the program/erase suspend mode, and requires the bank address. 17. the total number of cycles in the command sequence is determined by the number of words written to the write buffer. the max imum number of cycles in the command sequence is 37. 18. write buffer programming can be initiated after unlock bypass entry. 19. data is always output at the rising edge of clock. 20. do not enter wrong address or data cycles. 21. do not use 0x30 for cr data (otherwise in the erase suspend --> cr read or set sequence, the device will go into erase resum e instead of cr read or set). 22. software reset is needed after cr read (otherwise the device is still in cr read mode). 23. when device is in unlock bypass mode, do not enter ano ther command before unlock bypass reset command is issued). 24. configuration registers can not be programmed out of order. cr0 must be programmed prior to cr01 otherwise the configuratio n registers retain their previous settings. 80 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) legend x = don?t care table 11.2 sector protection commands command sequence (notes) cycles bus cycles 1 , 2 , 3 , 4 , 5 , 6 first second third fourth fifth sixth seventh addr data (10) addr data (10) addr data (10) addr data (10) addr data (10) addr data (10) addr data (10) secured silicon entry (5) 3 555 aa 2aa 55 555 88 program 4 555 aa 2aa 55 555 a0 pa pd read 1 00 data exit (7) 4 555 aa 2aa 55 555 90 xx 00 lock register register command set entry (5) 3 555 aa 2aa 55 555 40 register bits program (6) 2 xx a0 00 data register bits read 1 00 data register command set exit (7) 2xx 90 xx 00 password protection command set entry 3 555 aa 2aa 55 555 60 program (9) 2xx a0 00/ 01/ 02/03 pwd0/ 1/ 2/3/ read password (10) 400 pwd 0 01 pwd1 02 pwd 2 03 pwd 3 unlock (9) 700 25 00 03 00 pwd 0 01 pwd 1 02 pwd 2 03 pwd 3 00 29 protection command set exit 2 xx 90 xx 00 ppb non-volatile sector protection command set entry (5) 3 555 aa 2aa 55 (ba) 555 c0 program 2 xx a0 (ba) sa 00 all erase (8) 2xx 80 sa0 30 status read 1 (ba) sa rd(0) non-volatile sector protection command set exit (7) 2xx 90 xx 00 ppb lock bit global volatile sector protection freeze command set entry (5) 3 555 aa 2aa 55 555 50 set 2 xx a0 xx 00 status read 1 xx rd(0) global volatile sector protection freeze command set exit (7) 2xx 90 xx 00 dyb volatile sector protection command set entry (5) 3 555 aa 2aa 55 (ba) 555 e0 set 2 xx a0 (ba) sa 00 clear 2 xx a0 (ba) sa 01 status read 1 (ba) sa rd(0) volatile sector protection command set exit (7) 2xx 90 xx 00 accelerated program 2 555 a0 pa data sector erase 2 555 80 sa 30 asynchronous read 1 ra rd write to buffer 4 sa 25 sa wc pa pd wbl pd program buffer to flash 1 sa 29 february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 81 data sheet (advance information) ra = read address. rd = read data. pa = program address. addresses latch on the rising edge of th e avd# pulse or active edge of clk, whichever occurs first. pd = program data. data latches on the rising edg e of we# or ce# pulse, whichever occurs first. sa = sector address. ns128p = a22 ? a14, ns256p = a23 ? a14. ba = bank address. ns128p = a22 ? a20, and a19; ns256p = a23 ? a20. cr = configuration register data bits d15 ? d0. pwd3 ? pwd0 = password data. pd3 ? pd0 present four 16 bit combinations that represent the 64-bit password pwa = password address. address bits a1 and a0 are used to select each 16-bit portion of the 64-bit entity. pwd = password data. rd(0) = dq0 protection indicator bit. if protected, dq0 = 0, if unprotected, dq0 = 1. wbl = write buffer location. address must be within the same write buffer page as pa. wc = word count. number of write buffer locations to load minus 1. notes 1. see table 6.1 for description of bus operations. 2. all values are in hexadecimal. 3. except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cyc les of the autoselect commands, fourth cycle of the configuration register verify and password verify commands, and any cycle reading at rd(0) and rd(1). 4. data bits dq15 ? dq8 are don?t care in command sequences, except for rd, pd, wd, pwd, and pwd3 ? pwd0. 5. unless otherwise noted, address bits amax ? a14 are don?t cares. 6. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. the system must write the reset command to return the device to reading array data. 7. no unlock or command cycles required when bank is reading array data. 8. the data is 0000h for an unlocked sector and 0001h for a locked sector. 9. the exit command must be issued to reset the device into read mode, otherwise the device hangs. 10. data is always output at the rising edge of clock. 11.1 common flash memory interface the common flash in terface (cfi) specification outlines device and host system software in terrogation handshake, which allows specific vendor-specified soft -ware algorithms to be used for entire families of devices. software support can then be device-inde pendent, jedec id-independent, and forward-compatible and backward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address (ba)55h any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 11.3 ? 11.6 ) within that bank. all reads outside of the cfi address range, within the bank, returns non-valid data. reads from other banks ar e allowed, writes are not. to terminate reading cfi data, the system must wr ite the reset command. the following is a c source code example of using the cfi entry and exit f unctions. refer to the spansion low level driver user?s guide ( www.spansion.com ) for general information on spansion flash memory software development guidelines. /* example: cfi entry command */ *( (uint16 *)bank_addr + 0x0055 = 0x0098; /* write cfi entry command */ /* example: cfi exit command */ *( (uint16 *)bank_addr + 0x000 ) = 0x00f0; /* write cfi exit command */ for further information, pl ease refer to the cfi specification (s ee jedec publications jep137-a and jesd68.01and cfi publication 100). please contact yo ur sales office for copi es of these documents. 82 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) table 11.3 cfi query identification string addresses data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string qry 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists) table 11.4 system interface string addresses data description 1bh 0017h v cc min. (write/erase) d7 ? d4: volt, d3 ? d0: 100 millivolt 1ch 0019h v cc max. (write/erase) d7 ? d4: volt, d3 ? d0: 100 millivolt 1dh 0000h v pp min. voltage (00h = no v pp pin present) 1eh 0000h v pp max. voltage (00h = no v pp pin present) 1fh 0005h typical program time per single word write 2 n s (for example, 30 s) 20h 0009h typical program time using buffer 2 n s (for example, 300us) (00h = not supported) 21h 000ah typical time for sector erase 2 n ms 22h 0000h typical time for full chip erase 2 n ms (00h = not supported) 23h 0003h max. program time per single word [2 n times typical value] 24h 0002h max. program time using buffer [2 n times typical value] 25h 0002h max. time for sector erase [2 n times typical value] 26h 0000h max. time for full chip erase [2 n times typical value] (00h = not supported) table 11.5 device geometry definition (sheet 1 of 2) addresses data description 27h 0018h (ns128p) 0019h (ns256p) 001ah (ns512p) device size = 2 n byte 28h 29h 0001h 0000h flash device interface 0h=x8; 1h=x16; 2h=x8/x16; 3h=x32 [lower byte] [upper byte] (00h = not supported) 2ah 2bh 0006h 0000h max. number of bytes in multi-byte buffer write = 2 n [lower byte] [upper byte] (00h = not supported) 2ch 0002h (ns128p) 0002h (ns256p) 0001h (ns512p) number of erase block regions within device 01h = uniform sector; 02h = boot + uniform; 03h = boot + uniform + boot 2dh 007eh (ns128p) 00feh (ns256p) 01ffh (ns512p) erase block region 1 information (large sector section) [lower byte] ? number of sectors. 00h=1 sector; 01h=2 sectors... 03h=4 sectors [upper byte] [lower byte] ? equation =>(n = density in bytes of any 1 sector/256)h [upper byte] 2eh 0000h 2fh 0000h 30h 0002h 31h 0003h (ns128p) 0003h (ns256p) 0000h (ns512p) erase block region 2 information (small sector section) [lower byte] ? number of sectors. [upper byte] [lower byte] ? equation =>(n = density in bytes of any 1 sector/256)h [upper byte] 32h 0000h 33h 0080h (ns128p) 0080h (ns256p) 0000h (ns512p) 34h 0000h february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 83 data sheet (advance information) 35h 36h 37h 38h 0000h 0000h 0000h 0000h erase block region 3 information [lower byte] ? number of sectors. 00h=1 sector; 01h=2 sectors... 03h=4 sectors [upper byte] [lower byte] ? equation =>(n = density in bytes of any 1 sector/256)h [upper byte] 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information table 11.6 primary vendor-specific exte nded query (sheet 1 of 2) addresses data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string pri 43h 0031h major cfi version number, ascii 44h 0034h minor cfi version number, ascii 45h 0014h address sensitive unlock (bits 1 ? 0) 00b = required, 01b = not required silicon technology (bits 5 ? 2) 0011b = 130 nm; 0100b = 110 nm; 0101b = 90 nm 001010b = 000ah 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0001h sector protection per group 0 = not supported, x = number of sectors in per group 48h 0000h sector temporary unprotect 00 = not supported, 01 = supported 49h 0008h sector protect/unprotect scheme 08h = advanced sector protection; 07h = new sector protection scheme 4ah 0078h (ns128p) 00f0h (ns256p) 01e0h (ns512p) simultaneous operation number of sectors in all banks except bank0 4bh 0001h burst mode type 00 = not supported, 01 = supported 4ch 0000h not supported 4dh 0085h v pp (acceleration) supply minimum 00h = not supported, d7 ? d4: volt, d3 ? d0: 100 mv 4eh 0095h v pp (acceleration) supply maximum 00h = not supported, d7 ? d4: volt, d3 ? d0: 100 mv 4fh 0003h (ns128p) 0003h (ns256p) 0005h (ns512p) write protect function 00h = no boot, 01h = dual boot, 02h = bottom boot, 03h = top boot, 04h = uniform bottom, 05h = uniform top, 06h = all sectors 50h 0001h program suspend. 00h = not supported 51h 0001h unlock bypass 00 = not supported, 01=supported 52h 0008h secured silicon sector (customer otp area) size 2 n bytes 53h 0014h hardware reset low time-out during an embedded algorithm to read mode maximum 2 n ns (for example, 10 s => n=14) 54h 0014h hardware reset low time-out not during an embedded algorithm to read mode maximum 2 n ns (for example, 10 s => n=14) 55h 0005h erase suspend time-out maximum 2 n s 56h 0005h program suspend time-out maximum 2 n s 57h 0010h bank organization: x = number of banks 58h 0008h (ns128p) 0010h (ns256p) 0020h (ns512p) bank 0 region information. x = number of sectors in bank table 11.5 device geometry definition (sheet 2 of 2) addresses data description 84 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) 59h 0008h (ns128p) 0010h (ns256p) 0020h (ns512p) bank 1 region information. x = number of sectors in bank 5ah 0008h (ns128p) 0010h (ns256p) 0020h (ns512p) bank 2 region information. x = number of sectors in bank 5bh 0008h (ns128p) 0010h (ns256p) 0020h (ns512p) bank 3 region information. x = number of sectors in bank 5ch 0008h (ns128p) 0010h (ns256p) 0020h (ns512p) bank 4 region information. x = number of sectors in bank 5dh 0008h (ns128p) 0010h (ns256p) 0020h (ns512p) bank 5 region information. x = number of sectors in bank 5eh 0008h (ns128p) 0010h (ns256p) 0020h (ns512p) bank 6 region information. x = number of sectors in bank 5fh 0008h (ns128p) 0010h (ns256p) 0020h (ns512p) bank 7 region information. x = number of sectors in bank 60h 0008h (ns128p) 0010h (ns256p) 0020h (ns512p) bank 8 region information. x = number of sectors in bank 61h 0008h (ns128p) 0010h (ns256p) 0020h (ns512p) bank 9 region information. x = number of sectors in bank 62h 0008h (ns128p) 0010h (ns256p) 0020h (ns512p) bank 10 region information. x = number of sectors in bank 63h 0008h (ns128p) 0010h (ns256p) 0020h (ns512p) bank 11 region information. x = number of sectors in bank 64h 0008h (ns128p) 0010h (ns256p) 0020h (ns512p) bank 12 region information. x = number of sectors in bank 65h 0008h (ns128p) 0010h (ns256p) 0020h (ns512p) bank 13 region information. x = number of sectors in bank 66h 0008h (ns128p) 0010h (ns256p) 0020h (ns512p) bank 14 region information. x = number of sectors in bank 67h 000bh (ns128p) 0013h (ns256p) 0020h (ns512p) bank 15 region information. x = number of sectors in bank table 11.6 primary vendor-specific exte nded query (sheet 2 of 2) addresses data description february 20, 2007 S29NS-P_00_a1 S29NS-P mirrorbit tm flash family 85 data sheet (advance information) 12. revision history section description revision a (june 29, 2006) initial release revision a1 (february 20, 2007) global the tavds specification is changed from 4 ns to 5 ns the wait state for 83 mhz is changed to 8 icc3(max) is changed to 70 a and icc6(max) is changed to 40 a vil (min) is changed to -0.2 v toe (max) in both asynchronous & synchronous m odes is changed to 9 ns across all frequencies tcez (max) is changed to 10 ns across all frequencies toez (max) in both asynchronous & synchronous modes is changed to 10 ns across all frequencies tach(min) is changed to 6 ns (66 mhz) and 5 ns (83 mhz and 108 mhz) trdy(max) is changed to 10 ns tracc(max) is changed to 7.6 ns for 108 mhz toeh(min) in asynchronous mode is changed to 10 ns for 108 mhz erase and programing performance table is updated tce in asynchronous mode is changed to 83ns 86 S29NS-P mirrorbit tm flash family S29NS-P_00_a1 february 20, 2007 data sheet (advance information) colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, genera l office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for any use that includes fatal risks or dangers t hat, unless extremely high safety is secured, could have a s erious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic contro l, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intole rable (i.e., submersible repeater and artifi cial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abo ve-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect agains t injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document r epresent goods or technologies s ubject to certain restriction s on export under the foreign exchange and foreign trade law of japan, the us export ad ministration regulations or the applicable laws of any oth er country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subjec t to change without notice. this document ma y contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the informati on in this document is provided as is without warran ty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion assume s no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2005-2007 spansion inc. all rights reserved. spansion, the spansion logo, mirrorbit, ornand, hd-sim, and combinatio ns thereof are trademarks of spansion inc. other names are for informational purposes only and may be trademarks of their respecti ve owners. |
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